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| Freescale Semiconductor MPC885EC Rev. 3, 07/2004 MPC885/MPC880 Hardware Specifications This hardware specification contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC885/MPC880 (refer to Table 1 for the list of devices). The MPC885 is the superset device of the MPC885/MPC880 family. The CPU on the MPC885/MPC880 is a 32-bit PowerPCTM core that incorporates memory management units (MMUs) and instruction and data caches and that implements the PowerPC instruction set. 1 Overview The MPC885/880 is a versatile single-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications and communications and networking systems. The MPC885/MPC880 provides enhanced ATM functionality, an additional fast Ethernet controller, a USB, and an encryption block. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 15. 16. 17. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 9 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . 10 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Thermal Calculation and Measurement . . . . . . . . . . 12 Power Supply and Power Sequencing . . . . . . . . . . . 14 Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15 IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 44 CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 46 UTOPIA AC Electrical Specifications . . . . . . . . . . . 69 FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 71 Mechanical Data and Ordering Information . . . . . . . 75 Document Revision History . . . . . . . . . . . . . . . . . . . 89 (c) Freescale Semiconductor, Inc., 2004. All rights reserved. Features Table 1 shows the functionality supported by the members of the MPC885 family. Table 1. MPC885 Family Cache Part I Cache MPC885 MPC880 8 Kbyte 8 Kbyte D Cache 10BaseT 8 Kbyte 8 Kbyte Up to 3 Up to 2 10/100 2 2 3 2 2 2 1 1 Serial ATM and UTOPIA interface Serial ATM and UTOPIA interface Ethernet SCC SMC USB ATM Support Security Engine Yes No 2 Features The MPC885/880 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx core, a system integration unit (SIU), and a communications processor module (CPM). The following list summarizes the key MPC885/880 features: * * Embedded MPC8xx core up to 133 MHz Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode) -- The 133-MHz core frequency supports 2:1 mode only. -- The 66-/80-MHz core frequencies support both the 1:1 and 2:1 modes. Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two 32-bit general-purpose registers (GPRs) -- The core performs branch prediction with conditional prefetch and without conditional execution. -- 8-Kbyte data cache and 8-Kbyte instruction cache (see Table 1) - Instruction cache is two-way, set-associative with 256 sets in 2 blocks - Data cache is two-way, set-associative with 256 sets - Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks. - Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis. -- MMUs with 32-entry TLB, fully associative instruction and data TLBs -- MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and 16 protection groups -- Advanced on-chip emulation debug mode Provides enhanced ATM functionality found on the MPC862 and MPC866 families and includes the following: -- Improved operation, administration and maintenance (OAM) support -- OAM performance monitoring (PM) support -- Multiple APC priority levels available to support a range of traffic pace requirements -- Port-to-port switching capability without the need for RAM-based microcode -- Simultaneous MII (100BaseT) and UTOPIA (half- or full -duplex) capability -- Optional statistical cell counters per PHY * * MPC885/MPC880 Hardware Specifications, Rev. 3 2 Freescale Semiconductor Features * * * * * * * -- UTOPIA L2-compliant interface with added FIFO buffering to reduce the total cell transmission time and multi-PHY support. (The earlier UTOPIA L1 specification is also supported.) -- Parameter RAM for both SPI and I2C can be relocated without RAM-based microcode -- Supports full-duplex UTOPIA master (ATM side) and slave (PHY side) operations using a split bus -- AAL2/VBR functionality is ROM-resident. Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) 32 address lines Memory controller (eight banks) -- Contains complete dynamic RAM (DRAM) controller -- Each bank can be a chip select or RAS to support a DRAM bank. -- Up to 30 wait states programmable per memory bank -- Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices -- DRAM controller programmable to support most size and speed memory interfaces -- Four CAS lines, four WE lines, and one OE line -- Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) -- Variable block sizes (32 Kbyte-256 Mbyte) -- Selectable write protection -- On-chip bus arbitration logic General-purpose timers -- Four 16-bit timers or two 32-bit timers -- Gate mode can enable/disable counting. -- Interrupt can be masked on reference match and event capture Two fast Ethernet controllers (FEC)--Two 10/100 Mbps Ethernet/IEEE 802.3 CDMA/CS that interface through MII and/or RMII interfaces System integration unit (SIU) -- Bus monitor -- Software watchdog -- Periodic interrupt timer (PIT) -- Clock synthesizer -- Decrementer and time base -- Reset controller -- IEEE 1149.1 test access port (JTAG) Security engine is optimized to handle all the algorithms associated with IPsec, SSL/TLS, SRTP, 802.11i, and iSCSI processing. Available on the MPC885, the security engine contains a crypto-channel, a controller, and a set of crypto hardware accelerators (CHAs). The CHAs are: -- Data encryption standard execution unit (DEU) - DES, 3DES - Two key (K1, K2, K1) or three key (K1, K2, K3) - ECB and CBC modes for both DES and 3DES MPC885/MPC880 Hardware Specifications, Rev. 3 Freescale Semiconductor 3 Features * * -- Advanced encryption standard unit (AESU) - Implements the Rinjdael symmetric key cipher - ECB, CBC, and counter modes - 128-, 192-, and 256- bit key lengths -- Message digest execution unit (MDEU) - SHA with 160- or 256-bit message digest - MD5 with 128-bit message digest - HMAC with either algorithm -- Crypto-channel supporting multi-command descriptor chains -- Integrated controller managing internal resources and bus mastering -- Buffer size of 256 bytes for the DEU, AESU, and MDEU, with flow control for large data sizes Interrupts -- Six external interrupt request (IRQ) lines -- 12 port pins with interrupt capability -- 23 internal interrupt sources -- Programmable priority between SCCs -- Programmable highest priority request Communications processor module (CPM) -- RISC controller -- Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and RESTART TRANSMIT) * * * -- Supports continuous mode transmission and reception on all serial channels -- 8-Kbytes of dual-port RAM -- Several serial DMA (SDMA) channels to support the CPM -- Three parallel I/O registers with open-drain capability On-chip 16 x 16 multiply accumulate controller (MAC) -- One operation per clock (two-clock latency, one-clock blockage) -- MAC operates concurrently with other instructions -- FIR loop--Four clocks per four multiplies Four baud rate generators -- Independent (can be connected to any SCC or SMC) -- Allow changes during operation -- Autobaud support option Up to three serial communication controllers (SCCs) supporting the following protocols: -- Serial ATM capability on SCCs -- Optional UTOPIA port on SCC4 -- Ethernet/IEEE 802.3 optional on the SCC(s) supporting full 10-Mbps operation -- HDLC/SDLC -- HDLC bus (implements an HDLC-based local area network (LAN)) -- Asynchronous HDLC to support point-to-point protocol (PPP) MPC885/MPC880 Hardware Specifications, Rev. 3 4 Freescale Semiconductor Features * * * * * -- AppleTalk -- Universal asynchronous receiver transmitter (UART) -- Synchronous UART -- Serial infrared (IrDA) -- Binary synchronous communication (BISYNC) -- Totally transparent (bit streams) -- Totally transparent (frame based with optional cyclic redundancy check (CRC)) Up to two serial management channels (SMCs) supporting the following protocols: -- UART (low-speed operation) -- Transparent -- General circuit interface (GCI) controller -- Provide management for BRI devices as GCI controller in time-division multiplexed (TDM) channels Universal serial bus (USB)--Supports operation as a USB function endpoint, a USB host controller, or both for testing purposes (loop-back diagnostics) -- USB 2.0 full-/low-speed compatible -- The USB function mode has the following features: - Four independent endpoints support control, bulk, interrupt, and isochronous data transfers. - CRC16 generation and checking - CRC5 checking - NRZI encoding/decoding with bit stuffing - 12- or 1.5-Mbps data rate - Flexible data buffers with multiple buffers per frame - Automatic retransmission upon transmit error -- The USB host controller has the following features: - Supports control, bulk, interrupt, and isochronous data transfers - CRC16 generation and checking - NRZI encoding/decoding with bit stuffing - Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and data rate configuration). Note that low-speed operation requires an external hub. - Flexible data buffers with multiple buffers per frame - Supports local loop back mode for diagnostics (12 Mbps only) Serial peripheral interface (SPI) -- Supports master and slave modes -- Supports multiple-master operation on the same bus Inter-integrated circuit (I2C) port -- Supports master and slave modes -- Supports a multiple-master environment Time-slot assigner (TSA) -- Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation -- Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined MPC885/MPC880 Hardware Specifications, Rev. 3 Freescale Semiconductor 5 Features * * * * * * -- 1- or 8-bit resolution -- Allows independent transmit and receive routing, frame synchronization, and clocking -- Allows dynamic changes -- Can be internally connected to four serial channels (two SCCs and two SMCs) Parallel interface port (PIP) -- Centronics interface support -- Supports fast connection between compatible ports on MPC885/880 and other MPC8xx devices PCMCIA interface -- Master (socket) interface, release 2.1-compliant -- Supports two independent PCMCIA sockets -- 8 memory or I/O windows supported Debug interface -- Eight comparators: four operate on instruction address, two operate on data address, and two operate on data -- Supports conditions: = < > -- Each watchpoint can generate a break point internally. Normal high and normal low power modes to conserve power 1.8-V core and 3.3-V I/O operation The MPC885/880 comes in a 357-pin ball grid array (PBGA) package. MPC885/MPC880 Hardware Specifications, Rev. 3 6 Freescale Semiconductor Features The MPC885 block diagram is shown in Figure 1. Instruction Bus Embedded MPC8xx Processor Core Load/Store Bus 8-Kbyte Instruction Cache Instruction MMU 32-Entry ITLB 8-Kbyte Data Cache Data MMU 32-Entry DTLB Slave/Master IF Unified Bus System Interface Unit (SIU) Memory Controller Internal External Bus Interface Bus Interface Unit Unit System Functions PCMCIA-ATA Interface Fast Ethernet Controller DMAs DMAs FIFOs 10/100 BaseT Media Access Control MIII/RMII Parallel I/O 4 Baud Rate Generators Parallel Interface Port Timers 4 Timers Security Engine Controller Channel AESU DEU MDEU Interrupt 8-Kbyte Controllers Dual-Port RAM 32-Bit RISC Controller and Program ROM Virtual IDMA and Serial DMAs USB SCC2 SCC3 SCC4/ UTOPIA SMC1 SMC2 SPI I2C Time Slot Assigner Serial Interface Figure 1. MPC885 Block Diagram MPC885/MPC880 Hardware Specifications, Rev. 3 Freescale Semiconductor 7 Features The MPC880 block diagram is shown in Figure 2. Instruction Bus Embedded MPC8xx Processor Core Load/Store Bus 8-Kbyte Instruction Cache Instruction MMU 32-Entry ITLB 8-Kbyte Data Cache Data MMU 32-Entry DTLB Slave/Master IF Unified Bus System Interface Unit (SIU) Memory Controller External Internal Bus Interface Bus Interface Unit Unit System Functions PCMCIA-ATA Interface Fast Ethernet Controller DMAs DMAs FIFOs 10/100 BaseT Media Access Control MIII/RMII Parallel I/O 4 Baud Rate Generators Parallel Interface Port Timers 4 Timers Interrupt 8-Kbyte Controllers Dual-Port RAM 32-Bit RISC Controller and Program ROM Virtual IDMA and Serial DMAs USB SCC3 SCC4/ UTOPIA SMC1 SMC2 SPI I2C Time Slot Assigner Serial Interface Figure 2. MPC880 Block Diagram MPC885/MPC880 Hardware Specifications, Rev. 3 8 Freescale Semiconductor Maximum Tolerated Ratings 3 Maximum Tolerated Ratings Table 2. Maximum Tolerated Ratings Rating Symbol VDDH VDDL VDDSYN Difference between VDDL and VDDSYN Value -0.3 to 4.0 -0.3 to 2.0 -0.3 to 2.0 <100 Unit V V V mV This section provides the maximum tolerated voltage and temperature ranges for the MPC885/880. Table 2 displays the maximum tolerated ratings, and Table 3 displays the operating temperatures. Supply voltage 1 Input voltage 2 Storage temperature range 1 The 2 Vin Tstg GND - 0.3 to VDDH -55 to +150 V C power supply of the device must start its ramp from 0.0 V. Functional operating conditions are provided with the DC electrical specifications in Table 6. Absolute maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage to the device. See Section 8, "Power Supply and Power Sequencing." Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than VDDH. This restriction applies to power up and normal operation (that is, if the MPC885/880 is unpowered, a voltage greater than 2.5 V must not be applied to its inputs). Table 3. Operating Temperatures Rating Temperature 1 (standard) Symbol TA(min) Tj(max) Temperature (extended) TA(min) Tj(max) 1 Minimum Value 0 95 -40 100 Unit C C C C temperatures are guaranteed as ambient temperature, TA. Maximum temperatures are guaranteed as junction temperature, Tj. This device contains circuitry protecting against damage due to high-static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VDD). MPC885/MPC880 Hardware Specifications, Rev. 3 Freescale Semiconductor 9 Thermal Characteristics 4 Thermal Characteristics Table 4. MPC885/880 Thermal Resistance Data Rating Junction-to-ambient 1 Natural convection Environment Single-layer board (1s) Four-layer board (2s2p) Airflow (200 ft/min) Single-layer board (1s) Four-layer board (2s2p) Junction-to-board 4 Junction-to-case 5 Table 4 shows the thermal characteristics for the MPC885/880. Symbol RJA 2 RJMA 3 Value 37 25 30 22 17 10 2 2 Unit C/W RJMA3 RJMA RJB RJC 3 Junction-to-package top 6 Natural convection Airflow (200 ft/min) JT JT temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance. 2 Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal. 3 Per JEDEC JESD51-6 with the board horizontal 4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5 Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed pad packages where the pad would be expected to be soldered, junction-to-case thermal resistance is a simulated value from the junction to the exposed pad without contact resistance. 6 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 1 Junction 5 Power Dissipation Table 5. Power Dissipation (PD) Die Revision Bus Mode CPU Frequency 66 MHz 1:1 0 2:1 1 Typical Table 5 provides information on power dissipation. The modes are 1:1, where CPU and bus speeds are equal, and 2:1, where CPU frequency is twice bus speed. Typical 1 310 350 430 Maximum 2 390 430 495 Unit mW mW mW 80 MHz 133 MHz power dissipation at VDDL = VDDSYN = 1.8 V, and VDDH is at 3.3 V. MPC885/MPC880 Hardware Specifications, Rev. 3 10 Freescale Semiconductor DC Characteristics 2 Maximum power dissipation at VDDL = VDDSYN= 1.9 V, and VDDH is at 3.5 V. NOTE The values in Table 5 represent VDDL-based power dissipation and do not include I/O power dissipation over VDDH. I/O power dissipation varies widely by application due to buffer current, depending on external circuitry. The VDDSYN power dissipation is negligible. 6 DC Characteristics Table 6. DC Electrical Specifications Characteristic Symbol VDDL (Core) VDDH (I/O) VDDSYN 1 Difference between VDDL and VDDSYN Min 1.7 3.135 1.7 -- Max 1.9 3.465 1.9 100 Unit V V V mV Table 6 provides the DC electrical characteristics for the MPC885/880. Operating voltage Input high voltage (all inputs except EXTAL and EXTCLK) 2 Input low voltage 3 EXTAL, EXTCLK input high voltage Input leakage current, Vin = 5.5 V (except TMS, TRST, DSCK and DSDI pins) for 5-V tolerant pins 2 Input leakage current, Vin = VDDH (except TMS, TRST, DSCK, and DSDI) Input leakage current, Vin = 0 V (except TMS, TRST, DSCK and DSDI pins) Input capacitance 4 Output high voltage, IOH = -2.0 mA, except XTAL and open-drain pins Output low voltage IOL = 2.0 mA (CLKOUT) IOL = 3.2 mA 5 IOL = 5.3 mA 6 IOL = 7.0 mA (TXD1/PA14, TXD2/PA12) IOL = 8.9 mA (TS, TA, TEA, BI, BB, HRESET, SRESET) 1 The 2 VIH VIL VIHC Iin IIn IIn Cin VOH VOL 2.0 GND 0.7*(VDD H) -- -- -- -- 2.4 -- 3.465 0.8 VDDH 100 10 10 20 -- 0.5 V V V A A A pF V V difference between VDDL and VDDSYN cannot be more than 100 mV. The signals PA[0:15], PB[14:31], PC[4:15], PD[3:15], PE(14:31), TDI, TDO, TCK, TRST, TMS, MII1_TXEN, MII_MDIO are 5-V tolerant. The minimum voltage is still 2.0 V. 3 V (max) for the I2C interface is 0.8 V rather than the 1.5 V as specified in the I2C standard. IL MPC885/MPC880 Hardware Specifications, Rev. 3 Freescale Semiconductor 11 Thermal Calculation and Measurement 4 Input 5 capacitance is periodically sampled. A(0:31), TSIZ0/REG, TSIZ1, D(0:31), IRQ(2:4), IRQ6, RD/WR, BURST, IP_B(3:7), PA(0:11), PA13, PA15, PB(14:31), PC(4:15), PD(3:15), PE(14:31), MII1_CRS, MII_MDIO, MII1_TXEN, MII1_COL. 6 BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:7), WE(0:3), BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1, GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A, CE2_A, OP(0:3) BADDR(28:30) 7 Thermal Calculation and Measurement NOTE The VDDSYN power dissipation is negligible. For the following discussions, PD= (VDDL x IDDL) + PI/O, where PI/O is the power dissipation of the I/O drivers. 7.1 Estimation with Junction-to-Ambient Thermal Resistance An estimation of the chip junction temperature, TJ, in C can be obtained from the following equation: TJ = TA + (RJA x PD) where: TA = ambient temperature C RJA = package junction-to-ambient thermal resistance (C/W) PD = power dissipation in package The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated that errors of a factor of two (in the quantity TJ-TA) are possible. 7.2 Estimation with Junction-to-Case Thermal Resistance Historically, thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: RJA = RJC + RCA where: RJA = junction-to-ambient thermal resistance (C/W) RJC = junction-to-case thermal resistance (C/W) RCA = case-to-ambient thermal resistance (C/W) RJC is device-related and cannot be influenced by the user. The user adjusts the thermal environment to affect the case-to-ambient thermal resistance, RCA. For instance, the user can change the airflow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This thermal model is most useful for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink to the ambient environment. For most packages, a better model is required. MPC885/MPC880 Hardware Specifications, Rev. 3 12 Freescale Semiconductor Thermal Calculation and Measurement 7.3 Estimation with Junction-to-Board Thermal Resistance A simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-resistor model consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. It has been observed that the thermal performance of most plastic packages and especially PBGA packages is strongly dependent on the board temperature; see Figure 3. Figure 3. Effect of Board Temperature Rise on Thermal Behavior If the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equation: TJ = TB + (RJB x PD) where: RJB = junction-to-board thermal resistance (C/W) TB = board temperature C PD = power dissipation in package If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. For this method to work, the board and board mounting must be similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground plane. 7.4 Estimation Using Simulation When the board temperature is not known, a thermal simulation of the application is needed. The simple two resistor model can be used with the thermal simulation of the application [2], or a more accurate and complex model of the package can be used in the thermal simulation. MPC885/MPC880 Hardware Specifications, Rev. 3 Freescale Semiconductor 13 Power Supply and Power Sequencing 7.5 Experimental Determination To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) where: JT = thermal characterization parameter TT = thermocouple temperature on top of package PD = power dissipation in package The thermal characterization parameter is measured per the JESD51-2 specification published by JEDEC using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. 7.6 References Semiconductor Equipment and Materials International 805 East Middlefield Rd Mountain View, CA 94043 MIL-SPEC and EIA/JESD (JEDEC) specifications (Available from Global Engineering Documents) JEDEC Specifications (415) 964-5111 800-854-7179 or 303-397-7956 http://www.jedec.org 1. C.E. Triplett and B. Joiner, "An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module," Proceedings of SemiTherm, San Diego, 1998, pp. 47-54. 2. B. Joiner and V. Adams, "Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling," Proceedings of SemiTherm, San Diego, 1999, pp. 212-220. 8 Power Supply and Power Sequencing This section provides design considerations for the MPC885/880 power supply. The MPC885/880 has a core voltage (VDDL) and PLL voltage (VDDSYN), which both operate at a lower voltage than the I/O voltage VDDH. The I/O section of the MPC885/880 is supplied with 3.3 V across VDDH and VSS (GND). The signals PA[0:15], PB[14:31], PC[4:15], PD[3:15], TDI, TDO, TCK, TRST_B, TMS, MII_TXEN, and MII_MDIO are 5-V tolerant. All inputs cannot be more than 2.5 V greater than VDDH. In addition, 5-V tolerant pins can not exceed 5.5 V and remaining input pins cannot exceed 3.465 V. This restriction applies to power up/down and normal operation. One consequence of multiple power supplies is that when power is initially applied the voltage rails ramp up at different rates. The rates depend on the nature of the power supply, the type of load on each power supply, and the manner in which different voltages are derived. The following restrictions apply: * * VDDL must not exceed VDDH during power up and power down. VDDL must not exceed 1.9 V, and VDDH must not exceed 3.465 V. MPC885/MPC880 Hardware Specifications, Rev. 3 14 Freescale Semiconductor Layout Practices These cautions are necessary for the long-term reliability of the part. If they are violated, the electrostatic discharge (ESD) protection diodes are forward-biased, and excessive current can flow through these diodes. If the system power supply design does not control the voltage sequencing, the circuit shown Figure 4 can be added to meet these requirements. The MUR420 Schottky diodes control the maximum potential difference between the external bus and core power supplies on power up, and the 1N5820 diodes regulate the maximum potential difference on power down. VDDH MUR420 VDDL 1N5820 Figure 4. Example Voltage Sequencing Circuit 9 Layout Practices Each VDD pin on the MPC885/880 should be provided with a low-impedance path to the board's supply. Each GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on chip. The VDD power supply should be bypassed to ground using at least four 0.1 F by-pass capacitors located as close as possible to the four sides of the package. Each board designed should be characterized and additional appropriate decoupling capacitors should be used if required. The capacitor leads and associated printed circuit traces connecting to chip VDD and GND should be kept to less than half an inch per capacitor lead. At a minimum, a four-layer board employing two inner layers as VDD and GND planes should be used. All output pins on the MPC885/880 have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VDD and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. For more information, please refer to the MPC885 User's Manual, Section 14.4.3, "Clock Synthesizer Power (VDDSYN, VSSSYN, VSSSYN1)". 10 Bus Signal Timing The maximum bus speed supported by the MPC885/880 is 80 MHz. Higher-speed parts must be operated in half-speed bus mode (for example, an MPC885/880 used at 133 MHz must be configured for a 66 MHz bus). Table 7 shows the frequency ranges for standard part frequencies in 1:1 bus mode, and Table 8 shows the frequency ranges for standard part frequencies in 2:1 bus mode. MPC885/MPC880 Hardware Specifications, Rev. 3 15 Freescale Semiconductor Bus Signal Timing Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode) Part Frequency 66 MHz Min Core frequency Bus frequency 40 40 Max 66.67 66.67 80 MHz Min 40 40 Max 80 80 Table 8. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode) Part Frequency 66 MHz Min Core frequency Bus frequency 40 20 Max 66.67 33.33 80 MHz Min 40 20 Max 80 40 133 MHz Min 40 20 Max 133 66 Table 9 provides the timings for the MPC885/880 at 33-, 40-, 66-, and 80-MHz bus operation. The timing for the MPC885/880 bus shown assumes a 50-pF load for maximum delays and a 0-pF load for minimum delays. CLKOUT assumes a 100-pF load maximum delay. Table 9. Bus Operation Timings 33 MHz Num Characteristic Min B1 B1a Bus period (CLKOUT), see Table 7 EXTCLK to CLKOUT phase skew - If CLKOUT is an integer multiple of EXTCLK, then the rising edge of EXTCLK is aligned with the rising edge of CLKOUT. For a non-integer multiple of EXTCLK, this synchronization is lost, and the rising edges of EXTCLK and CLKOUT have a continuously varying phase skew. CLKOUT frequency jitter peak-to-peak Frequency jitter on EXTCLK CLKOUT phase jitter peak-to-peak for OSCLK 15 MHz CLKOUT phase jitter peak-to-peak for OSCLK < 15 MHz B2 B3 B4 B5 CLKOUT pulse width low (MIN = 0.4 x B1, MAX = 0.6 x B1) CLKOUT pulse width high (MIN = 0.4 x B1, MAX = 0.6 x B1) CLKOUT rise time CLKOUT fall time -- -2 Max -- +2 Min -- -2 Max -- +2 Min -- -2 Max -- +2 Min -- -2 Max -- +2 ns ns 40 MHz 66 MHz 80 MHz Unit B1b B1c B1d -- -- -- -- 12.1 12.1 -- -- 1 0.50 4 5 18.2 18.2 4.00 4.00 -- -- -- - 10.0 10.0 -- -- 1 0.50 4 5 15.0 15.0 4.00 4.00 -- -- -- -- 6.1 6.1 -- -- 1 0.50 4 5 9.1 9.1 4.00 4.00 -- -- -- -- 5.0 5.0 -- -- 1 0.50 4 5 7.5 7.5 4.00 4.00 ns % ns ns ns ns ns ns MPC885/MPC880 Hardware Specifications, Rev. 3 16 Freescale Semiconductor Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B7 CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31) output hold (MIN = 0.25 x B1) CLKOUT to TSIZ(0:1), REG, RSV, BDIP, PTR output hold (MIN = 0.25 x B1) CLKOUT to BR, BG, FRZ, VFLS(0:1), VF(0:2) IWP(0:2), LWP(0:1), STS output hold (MIN = 0.25 x B1) CLKOUT to A(0:31), BADDR(28:30) RD/WR, BURST, D(0:31) valid (MAX = 0.25 x B1 + 6.3) CLKOUT to TSIZ(0:1), REG, RSV, AT(0:3) BDIP, PTR valid (MAX = 0.25 x B1 + 6.3) CLKOUT to BR, BG, VFLS(0:1), VF(0:2), IWP(0:2), FRZ, LWP(0:1), STS valid 4 (MAX = 0.25 x B1 + 6.3) CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31), TSIZ(0:1), REG, RSV, AT(0:3), PTR High-Z (MAX = 0.25 x B1 + 6.3) CLKOUT to TS, BB assertion (MAX = 0.25 x B1 + 6.0) CLKOUT to TA, BI assertion (when driven by the memory controller or PCMCIA interface) (MAX = 0.00 x B1 + 9.30 1) CLKOUT to TS, BB negation (MAX = 0.25 x B1 + 4.8) CLKOUT to TA, BI negation (when driven by the memory controller or PCMCIA interface) (MAX = 0.00 x B1 + 9.00) CLKOUT to TS, BB High-Z (MIN = 0.25 x B1) CLKOUT to TA, BI High-Z (when driven by the memory controller or PCMCIA interface) (MIN = 0.00 x B1 + 2.5) CLKOUT to TEA assertion (MAX = 0.00 x B1 + 9.00) CLKOUT to TEA High-Z (MIN = 0.00 x B1 + 2.50) TA, BI valid to CLKOUT (setup time) (MIN = 0.00 x B1 + 6.00) 7.60 Max -- Min 6.30 Max -- Min 3.80 Max -- Min 3.13 Max -- ns 40 MHz 66 MHz 80 MHz Unit B7a B7b 7.60 7.60 -- -- 6.30 6.30 -- -- 3.80 3.80 -- -- 3.13 3.13 -- -- ns ns B8 -- 13.80 -- 12.50 -- 10.00 -- 9.43 ns B8a B8b -- -- 13.80 13.80 -- -- 12.50 12.50 -- -- 10.00 10.00 -- -- 9.43 9.43 ns ns B9 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns B11 B11a 7.60 13.60 6.30 12.30 3.80 2.50 9.30 2.50 9.30 2.50 9.80 9.30 3.13 2.50 9.13 9.30 ns ns B12 B12a 7.60 12.30 6.30 2.50 9.00 2.50 11.00 9.00 3.80 2.50 8.50 9.00 3.13 2.5 7.92 9.00 ns ns B13 B13a 7.60 21.60 6.30 20.30 3.80 14.00 3.13 12.93 2.50 15.00 2.50 15.00 2.50 15.00 2.5 15.00 ns ns B14 B15 B16 2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns ns ns 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 6.00 -- 6.00 -- 6.00 -- 6 -- MPC885/MPC880 Hardware Specifications, Rev. 3 17 Freescale Semiconductor Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B16a B16b B17 B17a B18 B19 B20 B21 B22 B22a TEA, KR, RETRY, CR valid to CLKOUT (setup time) (MIN = 0.00 x B1 + 4.5) BB, BG, BR, valid to CLKOUT (setup time) 2 (4MIN = 0.00 x B1 + 0.00) CLKOUT to TA, TEA, BI, BB, BG, BR valid (hold time) (MIN = 0.00 x B1 + 1.00 3) CLKOUT to KR, RETRY, CR valid (hold time) (MIN = 0.00 x B1 + 2.00) D(0:31) valid to CLKOUT rising edge (setup time) 4 (MIN = 0.00 x B1 + 6.00) CLKOUT rising edge to D(0:31) valid (hold time) 4 (MIN = 0.00 x B1 + 1.00 5) D(0:31) valid to CLKOUT falling edge (setup time) 6 (MIN = 0.00 x B1 + 4.00) CLKOUT falling edge to D(0:31) valid (hold time) 6 (MIN = 0.00 x B1 + 2.00) 4.50 4.00 1.00 2.00 6.00 1.00 4.00 2.00 Max -- -- -- -- -- -- -- -- Min 4.50 4.00 1.00 2.00 6.00 1.00 4.00 2.00 Max -- -- -- -- -- -- -- -- Min 4.50 4.00 2.00 2.00 6.00 2.00 4.00 2.00 Max -- -- -- -- -- -- -- -- Min 4.50 4.00 2.00 2.00 6.00 2.00 4.00 2.00 Max -- -- -- -- -- -- -- -- 9.43 8.00 ns ns ns ns ns ns ns ns ns ns 40 MHz 66 MHz 80 MHz Unit CLKOUT rising edge to CS asserted 7.60 13.80 6.30 12.50 3.80 10.00 3.13 GPCM ACS = 00 (MAX = 0.25 x B1 + 6.3) CLKOUT falling edge to CS asserted GPCM ACS = 10, TRLX = 0 (MAX = 0.00 x B1 + 8.00) CLKOUT falling edge to CS asserted GPCM ACS = 11, TRLX = 0, EBDF = 0 (MAX = 0.25 x B1 + 6.3) CLKOUT falling edge to CS asserted GPCM ACS = 11, TRLX = 0, EBDF = 1 (MAX = 0.375 x B1 + 6.6) CLKOUT rising edge to CS negated GPCM read access, GPCM write access ACS = 00, TRLX = 0 and CSNT = 0 (MAX = 0.00 x B1 + 8.00) A(0:31) and BADDR(28:30) to CS asserted GPCM ACS = 10, TRLX = 0 (MIN = 0.25 x B1 - 2.00) A(0:31) and BADDR(28:30) to CS asserted GPCM ACS = 11 TRLX = 0 (MIN = 0.50 x B1 - 2.00) CLKOUT rising edge to OE, WE(0:3) asserted (MAX = 0.00 x B1 + 9.00) CLKOUT rising edge to OE negated (MAX = 0.00 x B1 + 9.00) -- 8.00 -- 8.00 -- 8.00 -- B22b 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns B22c 10.90 18.00 10.90 16.00 5.20 12.30 4.69 10.93 ns B23 2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns B24 5.60 -- 4.30 -- 1.80 -- 1.13 -- ns B24a 13.20 -- 10.50 -- 5.60 -- 4.25 -- ns B25 B26 -- 2.00 9.00 9.00 -- 2.00 9.00 9.00 -- 2.00 9.00 9.00 -- 2.00 9.00 9.00 ns ns MPC885/MPC880 Hardware Specifications, Rev. 3 18 Freescale Semiconductor Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B27 A(0:31) and BADDR(28:30) to CS asserted GPCM ACS = 10, TRLX = 1 (MIN = 1.25 x B1 - 2.00) A(0:31) and BADDR(28:30) to CS asserted GPCM ACS = 11, TRLX = 1 (MIN = 1.50 x B1 - 2.00) CLKOUT rising edge to WE(0:3) negated GPCM write access CSNT = 0 (MAX = 0.00 x B1 + 9.00) CLKOUT falling edge to WE(0:3) negated GPCM write access TRLX = 0, CSNT = 1, EBDF = 0 (MAX = 0.25 x B1 + 6.80) CLKOUT falling edge to CS negated GPCM write access TRLX = 0, CSNT = 1 ACS = 10 or ACS = 11, EBDF = 0 (MAX = 0.25 x B1 + 6.80) 35.90 Max -- Min 29.30 Max -- Min 16.90 Max -- Min 13.60 Max -- ns 40 MHz 66 MHz 80 MHz Unit B27a 43.50 -- 35.50 -- 20.70 -- 16.75 -- ns B28 -- 9.00 -- 9.00 -- 9.00 -- 9.00 ns B28a 7.60 14.30 6.30 13.00 3.80 10.50 3.13 9.93 ns B28b -- 14.30 -- 13.00 -- 10.50 -- 9.93 ns B28c CLKOUT falling edge to WE(0:3) negated 10.90 18.00 10.90 18.00 5.20 12.30 4.69 GPCM write access TRLX = 0, CSNT = 1 write access TRLX = 0, CSNT = 1, EBDF = 1 (MAX = 0.375 x B1 + 6.6) CLKOUT falling edge to CS negated GPCM write access TRLX = 0, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 1 (MAX = 0.375 x B1 + 6.6) WE(0:3) negated to D(0:31) High-Z GPCM write access, CSNT = 0, EBDF = 0 (MIN = 0.25 x B1 - 2.00) -- 18.00 -- 18.00 -- 12.30 -- 11.29 ns B28d 11.30 ns B29 5.60 -- 4.30 -- 1.80 -- 1.13 -- ns B29a WE(0:3) negated to D(0:31) High-Z GPCM 13.20 write access, TRLX = 0, CSNT = 1, EBDF = 0 (MIN = 0.50 x B1 - 2.00) CS negated to D(0:31) High-Z GPCM write access, ACS = 00, TRLX = 0 & CSNT = 0 (MIN = 0.25 x B1 - 2.00) 5.60 -- 10.50 -- 5.60 -- 4.25 -- ns B29b -- 4.30 -- 1.80 -- 1.13 -- ns B29c CS negated to D(0:31) High-Z GPCM write 13.20 access, TRLX = 0, CSNT = 1, ACS = 10, or ACS = 11 EBDF = 0 (MIN = 0.50 x B1 - 2.00) WE(0:3) negated to D(0:31) High-Z GPCM 43.50 write access, TRLX = 1, CSNT = 1, EBDF = 0 (MIN = 1.50 x B1 - 2.00) CS negated to D(0:31) High-Z GPCM write 43.50 access, TRLX = 1, CSNT = 1, ACS = 10, or ACS = 11 EBDF = 0 (MIN = 1.50 x B1 - 2.00) -- 10.50 -- 5.60 -- 4.25 -- ns B29d -- 35.50 -- 20.70 -- 16.75 -- ns B29e -- 35.50 -- 20.70 -- 16.75 -- ns MPC885/MPC880 Hardware Specifications, Rev. 3 19 Freescale Semiconductor Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B29f WE(0:3) negated to D(0:31) High-Z GPCM write access, TRLX = 0, CSNT = 1, EBDF = 1 (MIN = 0.375 x B1 - 6.30) CS negated to D(0:31) High-Z GPCM write access, TRLX = 0, CSNT = 1 ACS = 10 or ACS = 11, EBDF = 1 (MIN = 0.375 x B1 - 6.30) 5.00 Max -- Min 3.00 Max -- Min 0.00 Max -- Min 0.00 Max -- ns 40 MHz 66 MHz 80 MHz Unit B29g 5.00 -- 3.00 -- 0.00 -- 0.00 -- ns B29h WE(0:3) negated to D(0:31) High-Z GPCM 38.40 write access, TRLX = 1, CSNT = 1, EBDF = 1 (MIN = 0.375 x B1 - 3.30) CS negated to D(0:31) High-Z GPCM write 38.40 access, TRLX = 1, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 1 (MIN = 0.375 x B1 - 3.30) CS, WE(0:3) negated to A(0:31), BADDR(28:30) Invalid GPCM write access 7 (MIN = 0.25 x B1 - .00) 5.60 -- 31.10 -- 17.50 -- 13.85 -- ns B29i -- 31.10 -- 17.50 -- 13.85 -- ns B30 -- 4.30 -- 1.80 -- 1.13 -- ns B30a WE(0:3) negated to A(0:31), 13.20 BADDR(28:30) Invalid GPCM, write access, TRLX = 0, CSNT = 1, CS negated to A(0:31) invalid GPCM write access TRLX = 0, CSNT =1 ACS = 10, or ACS == 11, EBDF = 0 (MIN = 0.50 x B1 - 2.00) WE(0:3) negated to A(0:31) invalid GPCM 43.50 BADDR(28:30) invalid GPCM write access, TRLX = 1, CSNT = 1. CS negated to A(0:31) invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10, or ACS == 11 EBDF = 0 (MIN = 1.50 x B1 - 2.00) WE(0:3) negated to A(0:31), BADDR(28:30) invalid GPCM write access, TRLX = 0, CSNT = 1. CS negated to A(0:31) invalid GPCM write access, TRLX = 0, CSNT = 1 ACS = 10, ACS == 11, EBDF = 1 (MIN = 0.375 x B1 - 3.00) 8.40 -- 10.50 -- 5.60 -- 4.25 -- ns B30b -- 35.50 -- 20.70 -- 16.75 -- ns B30c -- 6.40 -- 2.70 -- 1.70 -- ns B30d 38.67 WE(0:3) negated to A(0:31), BADDR(28:30) invalid GPCM write access TRLX = 1, CSNT =1, CS negated to A(0:31) invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10 or 11, EBDF = 1 -- 31.38 -- 17.83 -- 14.19 -- ns MPC885/MPC880 Hardware Specifications, Rev. 3 20 Freescale Semiconductor Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B31 CLKOUT falling edge to CS valid, as requested by control bit CST4 in the corresponding word in the UPM (MAX = 0.00 x B1 + 6.00) CLKOUT falling edge to CS valid, as requested by control bit CST1 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.80) CLKOUT rising edge to CS valid, as requested by control bit CST2 in the corresponding word in the UPM (MAX = 0.00 x B1 + 8.00) CLKOUT rising edge to CS valid, as requested by control bit CST3 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.30) 1.50 Max 6.00 Min 1.50 Max 6.00 Min 1.50 Max 6.00 Min 1.50 Max 6.00 ns 40 MHz 66 MHz 80 MHz Unit B31a 7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns B31b 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns B31c 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.40 ns B31d 13.30 18.00 11.30 16.00 7.60 12.30 4.69 CLKOUT falling edge to CS valid, as requested by control bit CST1 in the corresponding word in the UPM EBDF = 1 (MAX = 0.375 x B1 + 6.6) CLKOUT falling edge to BS valid, as requested by control bit BST4 in the corresponding word in the UPM (MAX = 0.00 x B1 + 6.00) CLKOUT falling edge to BS valid, as requested by control bit BST1 in the corresponding word in the UPM, EBDF = 0 (MAX = 0.25 x B1 + 6.80) CLKOUT rising edge to BS valid, as requested by control bit BST2 in the corresponding word in the UPM (MAX = 0.00 x B1 + 8.00) CLKOUT rising edge to BS valid, as requested by control bit BST3 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.80) 1.50 6.00 1.50 6.00 1.50 6.00 1.50 11.30 ns B32 6.00 ns B32a 7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns B32b 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns B32c 7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns B32d 13.30 18.00 11.30 16.00 7.60 12.30 4.49 CLKOUT falling edge to BS valid, as requested by control bit BST1 in the corresponding word in the UPM, EBDF = 1 (MAX = 0.375 x B1 + 6.60) CLKOUT falling edge to GPL valid, as requested by control bit GxT4 in the corresponding word in the UPM (MAX = 0.00 x B1 + 6.00) 1.50 6.00 1.50 6.00 1.50 6.00 1.50 11.30 ns B33 6.00 ns MPC885/MPC880 Hardware Specifications, Rev. 3 21 Freescale Semiconductor Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B33a CLKOUT rising edge to GPL valid, as requested by control bit GxT3 in the corresponding word in the UPM (MAX = 0.25 x B1 + 6.80) A(0:31), BADDR(28:30), and D(0:31) to CS valid, as requested by control bit CST4 in the corresponding word in the UPM (MIN = 0.25 x B1 - 2.00) Max Min Max Min Max Min Max ns 40 MHz 66 MHz 80 MHz Unit 7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 B34 5.60 -- 4.30 -- 1.80 -- 1.13 -- ns B34a 13.20 A(0:31), BADDR(28:30), and D(0:31) to CS valid, as requested by control bit CST1 in the corresponding word in the UPM (MIN = 0.50 x B1 - 2.00) A(0:31), BADDR(28:30), and D(0:31) to CS valid, as requested by CST2 in the corresponding word in UPM (MIN = 0.75 x B1 - 2.00) A(0:31), BADDR(28:30) to CS valid, as requested by control bit BST4 in the corresponding word in the UPM (MIN = 0.25 x B1 - 2.00) A(0:31), BADDR(28:30), and D(0:31) to BS valid, as requested by BST1 in the corresponding word in the UPM (MIN = 0.50 x B1 - 2.00) 20.70 -- 10.50 -- 5.60 -- 4.25 -- ns B34b -- 16.70 -- 9.40 -- 6.80 -- ns B35 5.60 -- 4.30 -- 1.80 -- 1.13 -- ns B35a 13.20 -- 10.50 -- 5.60 -- 4.25 -- ns B35b 20.70 A(0:31), BADDR(28:30), and D(0:31) to BS valid, as requested by control bit BST2 in the corresponding word in the UPM (MIN = 0.75 x B1 - 2.00) A(0:31), BADDR(28:30), and D(0:31) to GPL valid, as requested by control bit GxT4 in the corresponding word in the UPM (MIN = 0.25 x B1 - 2.00) UPWAIT valid to CLKOUT falling edge 8 (MIN = 0.00 x B1 + 6.00) CLKOUT falling edge to UPWAIT valid 8 (MIN = 0.00 x B1 + 1.00) AS valid to CLKOUT rising edge 9 (MIN = 0.00 x B1 + 7.00) A(0:31), TSIZ(0:1), RD/WR, BURST, valid to CLKOUT rising edge (MIN = 0.00 x B1 + 7.00) TS valid to CLKOUT rising edge (setup time) (MIN = 0.00 x B1 + 7.00) 5.60 -- 16.70 -- 9.40 -- 7.40 -- ns B36 -- 4.30 -- 1.80 -- 1.13 -- ns B37 B38 B39 B40 6.00 1.00 7.00 7.00 -- -- -- -- 6.00 1.00 7.00 7.00 -- -- -- -- 6.00 1.00 7.00 7.00 -- -- -- -- 6.00 1.00 7.00 7.00 -- -- -- -- ns ns ns ns B41 7.00 -- 7.00 -- 7.00 -- 7.00 -- ns MPC885/MPC880 Hardware Specifications, Rev. 3 22 Freescale Semiconductor Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num Characteristic Min B42 B43 1 2 40 MHz Min 2.00 -- Max -- TBD 66 MHz Min 2.00 -- Max -- TBD 80 MHz Unit Min 2.00 -- Max -- TBD ns ns Max -- TBD CLKOUT rising edge to TS valid (hold time) (MIN = 0.00 x B1 + 2.00) AS negation to memory controller signals negation (MAX = TBD) 2.00 -- For part speeds above 50 MHz, use 9.80 ns for B11a. The timing required for BR input is relevant when the MPC885/880 is selected to work with the internal bus arbiter. The timing for BG input is relevant when the MPC885/880 is selected to work with the external bus arbiter. 3 For part speeds above 50 MHz, use 2 ns for B17. 4 The D(0:31) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is asserted. 5 For part speeds above 50 MHz, use 2 ns for B19. 6 The D(0:31) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only for read accesses controlled by chip-selects under control of the user-programmable machine (UPM) in the memory controller, for data beats where DLT3 = 1 in the RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) 7 The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0. 8 The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 20. 9 The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior specified in Figure 23. MPC885/MPC880 Hardware Specifications, Rev. 3 23 Freescale Semiconductor Bus Signal Timing Figure 5 provides the control timing diagram. CLKOUT 2.0 V 0.8 V A B Outputs 2.0 V 0.8 V 2.0 V 0.8 V A B Outputs 2.0 V 0.8 V D C Inputs 2.0 V 0.8 V 2.0 V 0.8 V D C Inputs 2.0 V 0.8 V 2.0 V 0.8 V 2.0 V 0.8 V 0.8 V 2.0 V A B C D Maximum output delay specification Minimum output hold time Minimum input setup time specification Minimum input hold time specification Figure 5. Control Timing Figure 6 provides the timing for the external clock. CLKOUT B1 B1 B4 B5 B3 B2 Figure 6. External Clock Timing MPC885/MPC880 Hardware Specifications, Rev. 3 24 Freescale Semiconductor Bus Signal Timing Figure 7 provides the timing for the synchronous output signals. CLKOUT B8 B7 Output Signals B8a B7a Output Signals B8b B7b Output Signals B9 B9 Figure 7. Synchronous Output Signals Timing Figure 8 provides the timing for the synchronous active pull-up and open-drain output signals. CLKOUT B13 B11 TS, BB B13 B11 TA, BI B14 B15 TEA B12 B12 Figure 8. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing MPC885/MPC880 Hardware Specifications, Rev. 3 25 Freescale Semiconductor Bus Signal Timing Figure 9 provides the timing for the synchronous input signals. CLKOUT B16 B17 TA, BI B16 B17 TEA, KR, RETRY, CR B16 B17 BB, BG, BR Figure 9. Synchronous Input Signals Timing Figure 10 provides normal case timing for input data. It also applies to normal read accesses under the control of the user-programmable machine (UPM) in the memory controller. CLKOUT B16 B17 TA B18 B19 D[0:31] Figure 10. Input Data Timing in Normal Case MPC885/MPC880 Hardware Specifications, Rev. 3 26 Freescale Semiconductor Bus Signal Timing Figure 11 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) CLKOUT TA B20 B21 D[0:31] Figure 11. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1 Figure 12 through Figure 15 provide the timing for the external bus read controlled by various GPCM factors. CLKOUT B11 TS B8 A[0:31] B22 CSx B25 OE B28 WE[0:3] B18 D[0:31] B19 B26 B23 B12 Figure 12. External Bus Read Timing (GPCM Controlled--ACS = 00) MPC885/MPC880 Hardware Specifications, Rev. 3 27 Freescale Semiconductor Bus Signal Timing CLKOUT B11 TS B8 A[0:31] B22 CSx B24 OE B18 D[0:31] B19 B25 B26 B23 B12 Figure 13. External Bus Read Timing (GPCM Controlled--TRLX = 0, ACS = 10) CLKOUT B11 TS B8 A[0:31] B22 CSx B24 OE B18 D[0:31] B19 B25 B26 B23 B22 B12 Figure 14. External Bus Read Timing (GPCM Controlled--TRLX = 0, ACS = 11) MPC885/MPC880 Hardware Specifications, Rev. 3 28 Freescale Semiconductor Bus Signal Timing CLKOUT B11 TS B8 A[0:31] B22 CSx B27 OE B27 B22 B22 D[0:31] B18 B19 B26 B23 B12 Figure 15. External Bus Read Timing (GPCM Controlled--TRLX = 1, ACS = 10, ACS = 11) MPC885/MPC880 Hardware Specifications, Rev. 3 29 Freescale Semiconductor Bus Signal Timing Figure 16 through Figure 18 provide the timing for the external bus write controlled by various GPCM factors. CLKOUT B11 TS B8 A[0:31] B22 CSx B25 WE[0:3] B26 OE B8 D[0:31] B9 B29 B29 B28 B23 B30 B12 Figure 16. External Bus Write Timing (GPCM Controlled--TRLX = 0, CSNT = 0) MPC885/MPC880 Hardware Specifications, Rev. 3 30 Freescale Semiconductor Bus Signal Timing CLKOUT B11 TS B8 A[0:31] B22 CSx B25 WE[0:3] B26 OE B8 D[0:31] B28 B28 B9 B29 B29f B29 B29 B28 B28 B23 B30 B30 B12 Figure 17. External Bus Write Timing (GPCM Controlled--TRLX = 0, CSNT = 1) MPC885/MPC880 Hardware Specifications, Rev. 3 31 Freescale Semiconductor Bus Signal Timing CLKOUT B11 TS B8 A[0:31] B22 CSx B25 WE[0:3] B26 OE B8 D[0:31] B28 B28 B29 B29 B29 B9 B29 B29i B28 B28 B23 B30 B30 B12 Figure 18. External Bus Write Timing (GPCM Controlled--TRLX = 1, CSNT = 1) MPC885/MPC880 Hardware Specifications, Rev. 3 32 Freescale Semiconductor Bus Signal Timing Figure 19 provides the timing for the external bus controlled by the UPM. CLKOUT B8 A[0:31] B31 B31 B31 CSx B34 B34 B34 B32 B32 B32 BS_A[0:3], BS_B[0:3] B35 B36 B35 B35 B33 GPL_A[0:5], GPL_B[0:5] B33 B32 B32 B31 B31 Figure 19. External Bus Timing (UPM-Controlled Signals) MPC885/MPC880 Hardware Specifications, Rev. 3 33 Freescale Semiconductor Bus Signal Timing Figure 20 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT B38 CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 20. Asynchronous UPWAIT Asserted Detection in UPM-Handled Cycles Timing Figure 21 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT B38 CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 21. Asynchronous UPWAIT Negated Detection in UPM-Handled Cycles Timing MPC885/MPC880 Hardware Specifications, Rev. 3 34 Freescale Semiconductor Bus Signal Timing Figure 22 provides the timing for the synchronous external master access controlled by the GPCM. CLKOUT B41 TS B40 A[0:31], TSIZ[0:1], R/W, BURST B22 CSx B42 Figure 22. Synchronous External Master Access Timing (GPCM Handled--ACS = 00) Figure 23 provides the timing for the asynchronous external master memory access controlled by the GPCM. CLKOUT B39 AS B40 A[0:31], TSIZ[0:1], R/W B22 CSx Figure 23. Asynchronous External Master Memory Access Timing (GPCM Controlled--ACS = 00) Figure 24 provides the timing for the asynchronous external master control signals negation. AS B43 CSx, WE[0:3], OE, GPLx, BS[0:3] Figure 24. Asynchronous External Master--Control Signals Negation Timing MPC885/MPC880 Hardware Specifications, Rev. 3 35 Freescale Semiconductor Bus Signal Timing Table 10 provides the interrupt timing for the MPC885/880. Table 10. Interrupt Timing All Frequencies Num Characteristic 1 Min I39 I40 I41 I42 I43 1 Unit Max ns ns ns ns -- IRQx valid to CLKOUT rising edge (setup time) IRQx hold time after CLKOUT IRQx pulse width low IRQx pulse width high IRQx edge-to-edge time 6.00 2.00 3.00 3.00 4 x TCLOCKOUT The I39 and I40 timings describe the testing conditions under which the IRQ lines are tested when being defined as level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLKOUT. The I41, I42, and I43 timings are specified to allow correct functioning of the IRQ lines detection circuitry and have no direct relation with the total system interrupt latency that the MPC885/880 is able to support. Figure 25 provides the interrupt detection timing for the external level-sensitive lines. CLKOUT I39 I40 IRQx Figure 25. Interrupt Detection Timing for External Level Sensitive Lines Figure 26 provides the interrupt detection timing for the external edge-sensitive lines. CLKOUT I41 IRQx I43 I43 I42 Figure 26. Interrupt Detection Timing for External Edge Sensitive Lines MPC885/MPC880 Hardware Specifications, Rev. 3 36 Freescale Semiconductor Bus Signal Timing Table 11 shows the PCMCIA timing for the MPC885/880. Table 11. PCMCIA Timing 33 MHz Num Characteristic Min A(0:31), REG valid to PCMCIA strobe asserted 1 (MIN = 0.75 x B1 - 2.00) A(0:31), REG valid to ALE negation1 (MIN = 1.00 x B1 - 2.00) CLKOUT to REG valid (MAX = 0.25 x B1 + 8.00) CLKOUT to REG invalid (MIN = 0.25 - B1 + 1.00) CLKOUT to CE1, CE2 asserted (MAX = 0.25 x B1 + 8.00) CLKOUT to CE1, CE2 negated (MAX = 0.25 x B1 + 8.00) CLKOUT to PCOE, IORD, PCWE, IOWR assert time (MAX = 0.00 x B1 + 11.00) CLKOUT to PCOE, IORD, PCWE, IOWR negate time (MAX = 0.00 x B1 + 11.00) CLKOUT to ALE assert time (MAX = 0.25 x B1 + 6.30) CLKOUT to ALE negate time (MAX = 0.25 x B1 + 8.00) PCWE, IOWR negated to D(0:31) invalid 1 (MIN = 0.25 x B1 - 2.00) WAITA and WAITB valid to CLKOUT rising edge1 (MIN = 0.00 x B1 + 8.00) CLKOUT rising edge to WAITA and WAITB invalid1 (MIN = 0.00 x B1 + 2.00) 20.70 Max -- Min 16.70 Max -- Min 9.40 Max -- Min 7.40 Max -- ns 40 MHz 66 MHz 80 MHz Unit P44 28.30 -- 23.00 -- 13.20 -- 10.50 -- ns P45 P46 P47 P48 P49 7.60 8.60 7.60 7.60 -- 15.60 -- 15.60 15.60 11.00 6.30 7.30 6.30 6.30 -- 14.30 -- 14.30 14.30 11.00 3.80 4.80 3.80 3.80 -- 11.80 -- 11.80 11.80 11.00 3.13 4.13 3.13 3.13 -- 11.13 -- 11.13 11.13 11.00 ns ns ns ns ns P50 2.00 11.00 2.00 11.00 2.00 11.00 2.00 11.00 ns P51 P52 P53 7.60 -- 5.60 13.80 15.60 -- 6.30 -- 4.30 12.50 14.30 -- 3.80 -- 1.80 10.00 11.80 -- 3.13 -- 1.13 9.40 11.13 -- ns ns ns P54 8.00 -- 8.00 -- 8.00 -- 8.00 -- ns P55 2.00 -- 2.00 -- 2.00 -- 2.00 -- ns P56 1 PSST = 1. Otherwise add PSST times cycle time. PSHT = 0. Otherwise add PSHT times cycle time. These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the PCMCIA current cycle. The WAITx assertion will be effective only if it is detected 2 cycles before the PSL timer expiration. See Chapter 16, "PCMCIA Interface," in the MPC885 PowerQUICC Family User's Manual. MPC885/MPC880 Hardware Specifications, Rev. 3 37 Freescale Semiconductor Bus Signal Timing Figure 27 provides the PCMCIA access cycle timing for the external bus read. CLKOUT TS P44 A[0:31] P46 REG P48 CE1/CE2 P50 PCOE, IORD P52 ALE B18 D[0:31] B19 P53 P52 P51 P49 P45 P47 Figure 27. PCMCIA Access Cycles Timing External Bus Read MPC885/MPC880 Hardware Specifications, Rev. 3 38 Freescale Semiconductor Bus Signal Timing Figure 28 provides the PCMCIA access cycle timing for the external bus write. CLKOUT TS P44 A[0:31] P46 REG P48 CE1/CE2 P50 PCWE, IOWR P52 ALE B8 D[0:31] B9 P53 P52 P51 P54 P49 P45 P47 Figure 28. PCMCIA Access Cycles Timing External Bus Write Figure 29 provides the PCMCIA WAIT signals detection timing. CLKOUT P55 P56 WAITx Figure 29. PCMCIA WAIT Signals Detection Timing MPC885/MPC880 Hardware Specifications, Rev. 3 39 Freescale Semiconductor Bus Signal Timing Table 12 shows the PCMCIA port timing for the MPC885/880. Table 12. PCMCIA Port Timing 33 MHz Num Characteristic Min P57 P58 P59 P60 1 OP2 40 MHz Min -- 21.70 5.00 1.00 Max 19.00 -- -- -- 66 MHz Min -- 14.40 5.00 1.00 Max 19.00 -- -- -- 80 MHz Unit Min -- 12.40 5.00 1.00 Max 19.00 -- -- -- ns ns ns ns Max 19.00 -- -- -- CLKOUT to OPx valid (MAX = 0.00 x B1 + 19.00) HRESET negated to OPx drive 1 (MIN = 0.75 x B1 + 3.00) IP_Xx valid to CLKOUT rising edge (MIN = 0.00 x B1 + 5.00) CLKOUT rising edge to IP_Xx invalid (MIN = 0.00 x B1 + 1.00) and OP3 only. -- 25.70 5.00 1.00 Figure 30 provides the PCMCIA output port timing for the MPC885/880. CLKOUT P57 Output Signals HRESET P58 OP2, OP3 Figure 30. PCMCIA Output Port Timing Figure 31 provides the PCMCIA input port timing for the MPC885/880. CLKOUT P59 P60 Input Signals Figure 31. PCMCIA Input Port Timing MPC885/MPC880 Hardware Specifications, Rev. 3 40 Freescale Semiconductor Bus Signal Timing Table 13 shows the debug port timing for the MPC885/880. Table 13. Debug Port Timing All Frequencies Num Characteristic Min D61 D62 D63 D64 D65 D66 D67 DSCK cycle time DSCK clock pulse width DSCK rise and fall times DSDI input data setup time DSDI data hold time DSCK low to DSDO data valid DSCK low to DSDO invalid 3 x TCLOCKO UT Unit Max 3.00 ns ns ns 15.00 2.00 ns ns 1.25 x TCLO CKOUT 0.00 8.00 5.00 0.00 0.00 Figure 32 provides the input timing for the debug port clock. DSCK D61 D61 D63 D62 D62 D63 Figure 32. Debug Port Clock Input Timing Figure 33 provides the timing for the debug port. DSCK D64 D65 DSDI D66 D67 DSDO Figure 33. Debug Port Timings MPC885/MPC880 Hardware Specifications, Rev. 3 41 Freescale Semiconductor Bus Signal Timing Table 14 shows the reset timing for the MPC885/880. Table 14. Reset Timing 33 MHz Num Characteristic Min CLKOUT to HRESET high impedance (MAX = 0.00 x B1 + 20.00) CLKOUT to SRESET high impedance (MAX = 0.00 x B1 + 20.00) RSTCONF pulse width (MIN = 17.00 x B1) -- Configuration data to HRESET rising edge setup time (MIN = 15.00 x B1 + 50.00) -- Max 20.00 Min -- Max 20.00 Min -- Max 20.00 Min -- Max 20.00 ns 40 MHz 66 MHz 80 MHz Unit R69 -- 20.00 -- 20.00 -- 20.00 -- 20.00 ns R70 R71 R72 R73 515.20 -- 504.50 -- -- -- 425.00 -- 425.00 -- -- -- 257.60 -- 277.30 -- -- -- 212.50 -- 237.50 -- -- -- ns -- ns R74 Configuration data to RSTCONF 350.00 rising edge setup time (MIN = 0.00 x B1 + 350.00) Configuration data hold time after RSTCONF negation (MIN = 0.00 x B1 + 0.00) Configuration data hold time after HRESET negation (MIN = 0.00 x B1 + 0.00) HRESET and RSTCONF asserted to data out drive (MAX = 0.00 x B1 + 25.00) RSTCONF negated to data out high impedance (MAX = 0.00 x B1 + 25.00) CLKOUT of last rising edge before chip three-states HRESET to data out high impedance (MAX = 0.00 x B1 + 25.00) DSDI, DSCK setup (MIN = 3.00 x B1) DSDI, DSCK hold time (MIN = 0.00 x B1 + 0.00) SRESET negated to CLKOUT rising edge for DSDI and DSCK sample (MIN = 8.00 x B1) 0.00 -- 350.00 -- 350.00 -- 350.00 -- ns -- 0.00 -- 0.00 -- 0.00 -- ns R75 0.00 -- 0.00 -- 0.00 -- 0.00 -- ns R76 -- 25.00 -- 25.00 -- 25.00 -- 25.00 ns R77 -- 25.00 -- 25.00 -- 25.00 -- 25.00 ns R78 -- 25.00 -- 25.00 -- 25.00 -- 25.00 ns R79 R80 R81 90.90 0.00 242.40 -- -- -- 75.00 0.00 200.00 -- -- -- 45.50 0.00 121.20 -- -- -- 37.50 0.00 100.00 -- -- -- ns ns ns R82 MPC885/MPC880 Hardware Specifications, Rev. 3 42 Freescale Semiconductor Bus Signal Timing Figure 34 shows the reset timing for the data bus configuration. HRESET R71 R76 RSTCONF R73 R74 D[0:31] (IN) R75 Figure 34. Reset Timing--Configuration from Data Bus Figure 35 provides the reset timing for the data bus weak drive during configuration. CLKOUT R69 HRESET R79 RSTCONF R77 D[0:31] (OUT) (Weak) R78 Figure 35. Reset Timing--Data Bus Weak Drive During Configuration MPC885/MPC880 Hardware Specifications, Rev. 3 43 Freescale Semiconductor IEEE 1149.1 Electrical Specifications Figure 36 provides the reset timing for the debug port configuration. CLKOUT R70 R82 SRESET R80 R81 DSCK, DSDI R80 R81 Figure 36. Reset Timing--Debug Port Configuration 11 IEEE 1149.1 Electrical Specifications Table 15 provides the JTAG timings for the MPC885/880 shown in Figure 37 to Figure 40. Table 15. JTAG Timing All Frequencies Min J82 J83 J84 J85 J86 J87 J88 J89 J90 J91 J92 J93 J94 J95 J96 TCK cycle time TCK clock pulse width measured at 1.5 V TCK rise and fall times TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO data invalid TCK low to TDO high impedance TRST assert time TRST setup time to TCK low TCK falling edge to output valid TCK falling edge to output valid out of high impedance TCK falling edge to output high impedance Boundary scan input valid to TCK rising edge TCK rising edge to boundary scan input invalid 100.00 40.00 0.00 5.00 25.00 -- 0.00 -- 100.00 40.00 -- -- -- 50.00 50.00 Max -- -- 10.00 -- -- 27.00 -- 20.00 -- -- 50.00 50.00 50.00 -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Num Characteristic Unit MPC885/MPC880 Hardware Specifications, Rev. 3 44 Freescale Semiconductor IEEE 1149.1 Electrical Specifications TCK J82 J82 J84 J83 J83 J84 Figure 37. JTAG Test Clock Input Timing TCK J85 J86 TMS, TDI J87 J88 TDO J89 Figure 38. JTAG Test Access Port Timing Diagram TCK J91 J90 TRST Figure 39. JTAG TRST Timing Diagram MPC885/MPC880 Hardware Specifications, Rev. 3 45 Freescale Semiconductor CPM Electrical Characteristics TCK J92 Output Signals J93 Output Signals J95 Output Signals J96 J94 Figure 40. Boundary Scan (JTAG) Timing Diagram 12 CPM Electrical Characteristics This section provides the AC and DC electrical specifications for the communications processor module (CPM) of the MPC885/880. 12.1 PIP/PIO AC Electrical Specifications Table 16 provides the PIP/PIO AC timings as shown in Figure 41 to Figure 45. Table 16. PIP/PIO Timing All Frequencies Num Characteristic Min 21 22 23 24 25 26 27 28 29 30 31 Data-in setup time to STBI low Data-In hold time to STBI high STBI pulse width STBO pulse width Data-out setup time to STBO low Data-out hold time from STBO high STBI low to STBO low (Rx interlock) STBI low to STBO high (Tx interlock) Data-in setup time to clock high Data-in hold time from clock high Clock low to data-out valid (CPU writes data, control, or direction) 0 0 1.5 1 clk - 5 ns 2 5 -- 2 15 7.5 -- Max -- -- -- -- -- -- 4.5 -- -- -- 25 ns clk clk ns clk clk clk clk ns ns ns Unit MPC885/MPC880 Hardware Specifications, Rev. 3 46 Freescale Semiconductor CPM Electrical Characteristics DATA-IN 21 23 STBI 27 24 STBO 22 Figure 41. PIP Rx (Interlock Mode) Timing Diagram DATA-OUT 25 24 STBO (Output) 28 23 STBI (Input) 26 Figure 42. PIP Tx (Interlock Mode) Timing Diagram DATA-IN 21 23 STBI (Input) 22 24 STBO (Output) Figure 43. PIP Rx (Pulse Mode) Timing Diagram MPC885/MPC880 Hardware Specifications, Rev. 3 47 Freescale Semiconductor CPM Electrical Characteristics DATA-OUT 25 24 STBO (Output) 26 23 STBI (Input) Figure 44. PIP TX (Pulse Mode) Timing Diagram CLKO 29 30 DATA-IN 31 DATA-OUT Figure 45. Parallel I/O Data-In/Data-Out Timing Diagram 12.2 Port C Interrupt AC Electrical Specifications Table 17 provides the timings for port C interrupts. Table 17. Port C Interrupt Timing 33.34 MHz Num Characteristic Min 35 36 Port C interrupt pulse width low (edge-triggered mode) Port C interrupt minimum time between active edges 55 55 Max -- -- ns ns Unit MPC885/MPC880 Hardware Specifications, Rev. 3 48 Freescale Semiconductor CPM Electrical Characteristics Figure 46 shows the port C interrupt detection timing. 36 Port C (Input) 35 Figure 46. Port C Interrupt Detection Timing 12.3 IDMA Controller AC Electrical Specifications Table 18 provides the IDMA controller timings as shown in Figure 47 to Figure 50. Table 18. IDMA Controller Timing All Frequencies Num Characteristic Min 40 41 42 43 44 45 46 1 Applies Unit Max -- -- 12 12 20 15 -- ns ns ns ns ns ns ns DREQ setup time to clock high DREQ hold time from clock high 1 SDACK assertion delay from clock high SDACK negation delay from clock low SDACK negation delay from TA low SDACK negation delay from clock high TA assertion to falling edge of the clock setup time (applies to external TA) to high-to-low mode (EDM=1) 7 TBD -- -- -- -- 7 CLKO (Output) 41 40 DREQ (Input) Figure 47. IDMA External Requests Timing Diagram MPC885/MPC880 Hardware Specifications, Rev. 3 49 Freescale Semiconductor CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) 42 DATA 46 TA (Input) 43 SDACK Figure 48. SDACK Timing Diagram--Peripheral Write, Externally-Generated TA CLKO (Output) TS (Output) R/W (Output) 42 DATA 44 TA (Output) SDACK Figure 49. SDACK Timing Diagram--Peripheral Write, Internally-Generated TA MPC885/MPC880 Hardware Specifications, Rev. 3 50 Freescale Semiconductor CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) 42 DATA 45 TA (Output) SDACK Figure 50. SDACK Timing Diagram--Peripheral Read, Internally-Generated TA 12.4 Baud Rate Generator AC Electrical Specifications Table 19 provides the baud rate generator timings as shown in Figure 51. Table 19. Baud Rate Generator Timing All Frequencies Num Characteristic Min 50 51 52 BRGO rise and fall time BRGO duty cycle BRGO cycle -- 40 40 Max 10 60 -- ns % ns Unit 50 BRGOX 51 52 50 51 Figure 51. Baud Rate Generator Timing Diagram MPC885/MPC880 Hardware Specifications, Rev. 3 51 Freescale Semiconductor CPM Electrical Characteristics 12.5 Timer AC Electrical Specifications Table 20 provides the general-purpose timer timings as shown in Figure 52. Table 20. Timer Timing All Frequencies Num Characteristic Min 61 62 63 64 65 TIN/TGATE rise and fall time TIN/TGATE low time TIN/TGATE high time TIN/TGATE cycle time CLKO low to TOUT valid 10 1 2 3 3 Max -- -- -- -- 25 ns clk clk clk ns Unit CLKO 60 61 TIN/TGATE (Input) 61 65 TOUT (Output) 64 63 62 Figure 52. CPM General-Purpose Timers Timing Diagram 12.6 Serial Interface AC Electrical Specifications Table 21 provides the serial interface timings as shown in Figure 53 to Figure 57. Table 21. SI Timing All Frequencies Num Characteristic Min 70 71 71a 72 73 74 L1RCLK, L1TCLK frequency (DSC = 0) 1, 2 L1RCLK, L1TCLK width low (DSC = 0) 2 L1RCLK, L1TCLK width high (DSC = 0) 3 L1TXD, L1ST(1-4), L1RQ, L1CLKO rise/fall time L1RSYNC, L1TSYNC valid to L1CLK edge (SYNC setup time) L1CLK edge to L1RSYNC, L1TSYNC, invalid (SYNC hold time) -- P + 10 P + 10 -- 20.00 35.00 Max SYNCCLK /2.5 -- -- 15.00 -- -- MHz ns ns ns ns ns Unit MPC885/MPC880 Hardware Specifications, Rev. 3 52 Freescale Semiconductor CPM Electrical Characteristics Table 21. SI Timing (continued) All Frequencies Num Characteristic Min 75 76 77 78 78A 79 80 80A 81 82 L1RSYNC, L1TSYNC rise/fall time L1RXD valid to L1CLK edge (L1RXD setup time) L1CLK edge to L1RXD invalid (L1RXD hold time) L1CLK edge to L1ST(1-4) valid 4 Unit Max 15.00 -- -- 45.00 45.00 45.00 55.00 55.00 42.00 16.00 or SYNCCLK /2 -- -- 30.00 -- -- -- 0.00 ns ns ns ns ns ns ns ns ns MHz -- 17.00 13.00 10.00 10.00 10.00 10.00 L1SYNC valid to L1ST(1-4) valid L1CLK edge to L1ST(1-4) invalid L1CLK edge to L1TXD valid L1TSYNC valid to L1TXD valid 4 10.00 0.00 -- L1CLK edge to L1TXD high impedance L1RCLK, L1TCLK frequency (DSC =1) 83 83a 84 85 86 87 88 1 The L1RCLK, L1TCLK width low (DSC =1) L1RCLK, L1TCLK width high (DSC = 1)3 L1CLK edge to L1CLKO valid (DSC = 1) L1RQ valid before falling edge of L1TSYNC4 L1GR setup time2 P + 10 P + 10 -- 1.00 42.00 42.00 -- ns ns ns L1TCLK ns ns ns L1GR hold time L1CLK edge to L1SYNC valid (FSD = 00) CNT = 0000, BYT = 0, DSC = 0) ratio SyncCLK/L1RCLK must be greater than 2.5/1. specs are valid for IDL mode only. 3 Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns. 4 These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever comes later. 2 These MPC885/MPC880 Hardware Specifications, Rev. 3 53 Freescale Semiconductor CPM Electrical Characteristics L1RCLK (FE=0, CE=0) (Input) 71 72 L1RCLK (FE=1, CE=1) (Input) RFSD=1 75 L1RSYNC (Input) 73 74 L1RXD (Input) 76 78 L1ST(4-1) (Output) 79 BIT0 77 70 71a Figure 53. SI Receive Timing Diagram with Normal Clocking (DSC = 0) MPC885/MPC880 Hardware Specifications, Rev. 3 54 Freescale Semiconductor CPM Electrical Characteristics L1RCLK (FE=1, CE=1) (Input) 72 82 L1RCLK (FE=0, CE=0) (Input) RFSD=1 75 L1RSYNC (Input) 73 74 L1RXD (Input) 76 78 L1ST(4-1) (Output) 79 BIT0 77 83a 84 L1CLKO (Output) Figure 54. SI Receive Timing with Double-Speed Clocking (DSC = 1) MPC885/MPC880 Hardware Specifications, Rev. 3 55 Freescale Semiconductor CPM Electrical Characteristics L1TCLK (FE=0, CE=0) (Input) 71 72 L1TCLK (FE=1, CE=1) (Input) 73 TFSD=0 75 L1TSYNC (Input) 74 80a L1TXD (Output) BIT0 80 78 L1ST(4-1) (Output) 79 81 70 Figure 55. SI Transmit Timing Diagram (DSC = 0) MPC885/MPC880 Hardware Specifications, Rev. 3 56 Freescale Semiconductor CPM Electrical Characteristics L1RCLK (FE=0, CE=0) (Input) 72 82 L1RCLK (FE=1, CE=1) (Input) TFSD=0 75 L1RSYNC (Input) 73 74 L1TXD (Output) BIT0 80 78a L1ST(4-1) (Output) 78 84 L1CLKO (Output) 79 81 83a Figure 56. SI Transmit Timing with Double Speed Clocking (DSC = 1) MPC885/MPC880 Hardware Specifications, Rev. 3 57 Freescale Semiconductor 58 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 L1RCLK (Input) 73 71 CPM Electrical Characteristics L1RSYNC (Input) 71 74 B17 B16 72 77 B17 B16 B15 B14 B13 76 78 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M 81 B15 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M 80 L1TXD (Output) Figure 57. IDL Timing 85 L1RXD (Input) MPC885/MPC880 Hardware Specifications, Rev. 3 86 87 L1ST(4-1) (Output) L1RQ (Output) Freescale Semiconductor L1GR (Input) CPM Electrical Characteristics 12.7 SCC in NMSI Mode Electrical Specifications Table 22 provides the NMSI external clock timing. Table 22. NMSI External Clock Timing All Frequencies Num Characteristic Min 100 101 102 103 104 105 106 107 108 1 The 2 Also Unit Max -- -- 15.00 50.00 50.00 -- -- -- -- ns ns ns ns ns ns ns ns ns RCLK1 and TCLK1 width high 1 RCLK1 and TCLK1 width low RCLK1 and TCLK1 rise/fall time TXD1 active delay (from TCLK1 falling edge) RTS1 active/inactive delay (from TCLK1 falling edge) CTS1 setup time to TCLK1 rising edge RXD1 setup time to RCLK1 rising edge RXD1 hold time from RCLK1 rising edge 2 1/SYNCCLK 1/SYNCCLK + 5 -- 0.00 0.00 5.00 5.00 5.00 5.00 CD1 setup time to RCLK1 rising edge ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2.25/1. applies to CD and CTS hold time when they are used as external sync signals. Table 23 provides the NMSI internal clock timing. Table 23. NMSI Internal Clock Timing All Frequencies Num Characteristic Min 100 102 103 104 105 106 107 108 1 The 2 Also Unit Max SYNCCLK/3 -- 30.00 30.00 -- -- -- -- MHz ns ns ns ns ns ns ns RCLK1 and TCLK1 frequency 1 RCLK1 and TCLK1 rise/fall time TXD1 active delay (from TCLK1 falling edge) RTS1 active/inactive delay (from TCLK1 falling edge) CTS1 setup time to TCLK1 rising edge RXD1 setup time to RCLK1 rising edge RXD1 hold time from RCLK1 rising edge 2 CD1 setup time to RCLK1 rising edge 0.00 -- 0.00 0.00 40.00 40.00 0.00 40.00 ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 3/1. applies to CD and CTS hold time when they are used as external sync signals MPC885/MPC880 Hardware Specifications, Rev. 3 59 Freescale Semiconductor CPM Electrical Characteristics Figure 58 through Figure 60 show the NMSI timings. RCLK1 102 106 RxD1 (Input) 107 108 CD1 (Input) 102 101 100 107 CD1 (SYNC Input) Figure 58. SCC NMSI Receive Timing Diagram TCLK1 102 102 101 100 TxD1 (Output) 103 105 RTS1 (Output) 104 104 CTS1 (Input) 107 CTS1 (SYNC Input) Figure 59. SCC NMSI Transmit Timing Diagram MPC885/MPC880 Hardware Specifications, Rev. 3 60 Freescale Semiconductor CPM Electrical Characteristics TCLK1 102 102 101 100 TxD1 (Output) 103 RTS1 (Output) 104 105 CTS1 (Echo Input) 107 104 Figure 60. HDLC Bus Timing Diagram 12.8 Ethernet Electrical Specifications Table 24 provides the Ethernet timings as shown in Figure 61 to Figure 63. Table 24. Ethernet Timing All Frequencies Num Characteristic Min 120 121 122 123 124 125 126 127 128 129 130 131 132 133 CLSN width high RCLK1 rise/fall time RCLK1 width low RCLK1 clock period 1 RXD1 setup time RXD1 hold time RENA active delay (from RCLK1 rising edge of the last data bit) RENA width low TCLK1 rise/fall time TCLK1 width low TCLK1 clock period1 40 -- 40 80 20 5 10 100 -- 40 99 -- 6.5 10 Max -- 15 -- 120 -- -- -- -- 15 -- 101 50 50 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit TXD1 active delay (from TCLK1 rising edge) TXD1 inactive delay (from TCLK1 rising edge) TENA active delay (from TCLK1 rising edge) MPC885/MPC880 Hardware Specifications, Rev. 3 61 Freescale Semiconductor CPM Electrical Characteristics Table 24. Ethernet Timing (continued) All Frequencies Num Characteristic Min 134 138 139 1 2 Unit Max 50 20 20 ns ns ns TENA inactive delay (from TCLK1 rising edge) CLKO1 low to SDACK asserted 2 10 -- -- CLKO1 low to SDACK negated 2 The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2/1. SDACK is asserted whenever the SDMA writes the incoming frame DA into memory. CLSN(CTS1) (Input) 120 Figure 61. Ethernet Collision Timing Diagram RCLK1 121 124 RxD1 (Input) 125 126 127 RENA(CD1) (Input) 121 123 Last Bit Figure 62. Ethernet Receive Timing Diagram MPC885/MPC880 Hardware Specifications, Rev. 3 62 Freescale Semiconductor CPM Electrical Characteristics TCLK1 128 131 TxD1 (Output) 132 133 TENA(RTS1) (Input) 134 128 121 129 RENA(CD1) (Input) (NOTE 2) NOTES: 1. Transmit clock invert (TCI) bit in GSMR is set. 2. If RENA is negated before TENA or RENA is not asserted at all during transmit, then the CSL bit is set in the buffer descriptor at the end of the frame transmission. Figure 63. Ethernet Transmit Timing Diagram 12.9 SMC Transparent AC Electrical Specifications Table 25 provides the SMC transparent timings as shown in Figure 64. Table 25. SMC Transparent Timing All Frequencies Num SMCLK clock period 1 SMCLK width low SMCLK width high SMCLK rise/fall time SMTXD active delay (from SMCLK falling edge) SMRXD/SMSYNC setup time RXD1/SMSYNC hold time Characteristic Min 150 151 151A 152 153 154 155 1 Unit Max -- -- -- 15 50 -- -- ns ns ns ns ns ns ns 100 50 50 -- 10 20 5 SyncCLK must be at least twice as fast as SMCLK. MPC885/MPC880 Hardware Specifications, Rev. 3 63 Freescale Semiconductor CPM Electrical Characteristics SMCLK 152 152 151 151 150 SMTXD (Output) 154 155 SMSYNC 154 155 SMRXD (Input) NOTE: 1. This delay is equal to an integer number of character-length clocks. NOTE 153 Figure 64. SMC Transparent Timing Diagram 12.10SPI Master AC Electrical Specifications Table 26 provides the SPI master timings as shown in Figure 65 and Figure 66. Table 26. SPI Master Timing All Frequencies Num Characteristic Min 160 161 162 163 164 165 166 167 MASTER cycle time MASTER clock (SCK) high or low time MASTER data setup time (inputs) Master data hold time (inputs) Master data valid (after SCK edge) Master data hold time (outputs) Rise time output Fall time output 4 2 15 0 -- 0 -- -- Max 1024 512 -- -- 10 -- 15 15 tcyc tcyc ns ns ns ns ns ns Unit MPC885/MPC880 Hardware Specifications, Rev. 3 64 Freescale Semiconductor CPM Electrical Characteristics SPICLK (CI=0) (Output) 161 161 SPICLK (CI=1) (Output) 163 162 SPIMISO (Input) msb 166 Data 165 167 SPIMOSI (Output) msb Data lsb lsb 164 166 msb msb 167 167 160 166 Figure 65. SPI Master (CP = 0) Timing Diagram SPICLK (CI=0) (Output) 161 161 SPICLK (CI=1) (Output) 163 162 SPIMISO (Input) msb 166 Data 165 167 SPIMOSI (Output) msb Data lsb lsb 164 166 msb msb 167 167 160 166 Figure 66. SPI Master (CP = 1) Timing Diagram MPC885/MPC880 Hardware Specifications, Rev. 3 65 Freescale Semiconductor CPM Electrical Characteristics 12.11SPI Slave AC Electrical Specifications Table 27 provides the SPI slave timings as shown in Figure 67 and Figure 68. Table 27. SPI Slave Timing All Frequencies Num Characteristic Min 170 171 172 173 174 175 176 177 Slave cycle time Slave enable lead time Slave enable lag time Slave clock (SPICLK) high or low time Slave sequential transfer delay (does not require deselect) Slave data setup time (inputs) Slave data hold time (inputs) Slave access time 2 15 15 1 1 20 20 -- Max -- -- -- -- -- -- -- 50 tcyc ns ns tcyc tcyc ns ns ns Unit SPISEL (Input) 172 174 SPICLK (CI=0) (Input) 173 173 SPICLK (CI=1) (Input) 177 180 SPIMISO (Output) msb 175 176 SPIMOSI (Input) msb Data Data 179 181 182 lsb msb lsb 181 182 178 Undef msb 182 170 181 171 Figure 67. SPI Slave (CP = 0) Timing Diagram MPC885/MPC880 Hardware Specifications, Rev. 3 66 Freescale Semiconductor CPM Electrical Characteristics SPISEL (Input) 172 171 SPICLK (CI=0) (Input) 173 173 SPICLK (CI=1) (Input) 177 180 SPIMISO (Output) Undef 175 176 SPIMOSI (Input) msb msb 179 181 182 Data lsb msb Data lsb 182 178 msb 182 181 181 170 174 Figure 68. SPI Slave (CP = 1) Timing Diagram 12.12I2C AC Electrical Specifications Table 28 provides the I2C (SCL < 100 KHz) timings. Table 28. I2C Timing (SCL < 100 KHZ) All Frequencies Num Characteristic Min 200 200 202 203 204 205 206 207 208 209 SCL clock frequency (slave) SCL clock frequency (master) 1 0 1.5 4.7 4.7 4.0 4.7 4.0 0 250 -- Max 100 100 -- -- -- -- -- -- -- 1 KHz KHz s s s s s s ns s Unit Bus free time between transmissions Low period of SCL High period of SCL Start condition setup time Start condition hold time Data hold time Data setup time SDL/SCL rise time MPC885/MPC880 Hardware Specifications, Rev. 3 67 Freescale Semiconductor CPM Electrical Characteristics Table 28. I2C Timing (SCL < 100 KHZ) (continued) All Frequencies Num Characteristic Min 210 211 1 Unit Max 300 -- ns s SDL/SCL fall time Stop condition setup time -- 4.7 SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) x pre_scaler x 2). The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1. Table 29 provides the I2C (SCL > 100 KHz) timings. Table 29. I2C Timing (SCL > 100 KHZ) All Frequencies Num Characteristic Expression Min 200 200 202 203 204 205 206 207 208 209 210 211 1 SCL Unit Max BRGCLK/48 BRGCLK/48 -- -- -- -- -- -- -- 1/(10 x fSCL) 1/(33 x fSCL) -- Hz Hz s s s s s s s s s s SCL clock frequency (slave) SCL clock frequency (master) 1 Bus free time between transmissions Low period of SCL High period of SCL Start condition setup time Start condition hold time Data hold time Data setup time SDL/SCL rise time SDL/SCL fall time Stop condition setup time fSCL fSCL -- -- -- -- -- -- -- -- -- -- 0 BRGCLK/16512 1/(2.2 x fSCL) 1/(2.2 x fSCL) 1/(2.2 x fSCL) 1/(2.2 x fSCL) 1/(2.2 x fSCL) 0 1/(40 x fSCL) -- -- 1/2(2.2 x fSCL) frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) x pre_scaler x 2). The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1. MPC885/MPC880 Hardware Specifications, Rev. 3 68 Freescale Semiconductor UTOPIA AC Electrical Specifications Figure 69 shows the I2C bus timing. SDA 202 205 SCL 206 209 210 211 203 207 204 208 Figure 69. I2C Bus Timing Diagram 13 UTOPIA AC Electrical Specifications Table 30, Table 31, and Table 32, show the AC electrical specifications for the UTOPIA interface. Table 30. UTOPIA Master (Muxed Mode) Electrical Specifications Num U1 Signal Characteristic UtpClk rise/fall time (internal clock option) Duty cycle Frequency U2 U3 U4 UTPB, SOC, RxEnb, TxEnb, RxAddr, and TxAddr active delay (and PHREQ and PHSEL active delay in multi-PHY mode) UTPB, SOC, Rxclav and Txclav setup time UTPB, SOC, Rxclav and Txclav hold time Output Input Input 2 ns 4 ns 1 ns Direction Output 50 Min Max 4 ns 50 33 16 ns Unit ns % MHz ns ns ns Table 31. UTOPIA Master (Split Bus Mode) Electrical Specifications Num U1 Signal Characteristic UtpClk rise/fall time (Internal clock option) Duty cycle Frequency U2 U3 U4 UTPB, SOC, RxEnb, TxEnb, RxAddr and TxAddr active delay (PHREQ and PHSEL active delay in multi-PHY mode) UTPB_Aux, SOC_Aux, Rxclav and Txclav setup time UTPB_Aux, SOC_Aux, Rxclav and Txclav hold time Output Input Input 2 ns 4 ns 1 ns Direction Output 50 Min Max 4 ns 50 33 16 ns Unit ns % MHz ns ns ns MPC885/MPC880 Hardware Specifications, Rev. 3 69 Freescale Semiconductor UTOPIA AC Electrical Specifications Table 32. UTOPIA Slave (Split Bus Mode) Electrical Specifications Num U1 Signal Characteristic UtpClk rise/fall time (external clock option) Duty cycle Frequency U2 U3 U4 UTPB, SOC, Rxclav and Txclav active delay UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr setup time UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr hold time Output Input Input 2 ns 4 ns 1 ns Direction Input 40 Min Max 4 ns 60 33 16 ns Unit ns % MHz ns ns ns Figure 70 shows signal timings during UTOPIA receive operations. U1 UtpClk U2 PHREQn U3 3 RxClav High-Z at MPHY U2 2 U1 U4 4 High-Z at MPHY RxEnb UTPB SOC U3 3 U4 4 Figure 70. UTOPIA Receive Timing MPC885/MPC880 Hardware Specifications, Rev. 3 70 Freescale Semiconductor USB Electrical Characteristics Figure 71 shows signal timings during UTOPIA transmit operations. U1 1 UtpClk U2 5 PHSELn U3 3 TxClav High-Z at MPHY TxEnb UTPB SOC U2 2 High-Z at Multi-PHYP U4 4 U1 U2 5 Figure 71. UTOPIA Transmit Timing 14 USB Electrical Characteristics This section provides the AC timings for the USB interface. 14.1 USB Interface AC Timing Specifications The USB Port uses the transmit clock on SCC1. Table 33 lists the USB interface timings. Table 33. USB Interface AC Timing Specifications All Frequencies Name US1 Characteristic Min USBCLK frequency of operation 1 Low speed Full speed USBCLK duty cycle (measured at 1.5 V) 45 6 48 55 Max MHz MHz % Unit US4 1 USBCLK accuracy should be 500 ppm or better. USBCLK may be stopped to conserve power. 15 FEC Electrical Characteristics This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the timing specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V. MPC885/MPC880 Hardware Specifications, Rev. 3 71 Freescale Semiconductor FEC Electrical Characteristics 15.1 MII and Reduced MII Receive Signal Timing The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz + 1%. The reduced MII (RMII) receiver functions correctly up to a RMII_REFCLK maximum frequency of 50 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_RX_CLK frequency - 1%. Table 34 provides information on the MII and RMII receive signal timing. Table 34. MII Receive Signal Timing Num M1 M2 M3 M4 Characteristic MII_RXD[3:0], MII_RX_DV, MII_RX_ERR to MII_RX_CLK setup MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold MII_RX_CLK pulse width high MII_RX_CLK pulse width low Min 5 5 35% 35% 4 2 Max -- -- 65% 65% -- -- Unit ns ns MII_RX_CLK period MII_RX_CLK period ns ns M1_RMII RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR to RMII_REFCLK setup M2_RMII RMII_REFCLK to RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR hold Figure 72 shows MII receive signal timing. M3 MII_RX_CLK (input) M4 MII_RXD[3:0] (inputs) MII_RX_DV MII_RX_ER M1 M2 Figure 72. MII Receive Signal Timing Diagram 15.2 MII and Reduced MII Transmit Signal Timing The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz +1%. The RMII transmitter functions correctly up to a RMII_REFCLK maximum frequency of 50 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK frequency - 1%. MPC885/MPC880 Hardware Specifications, Rev. 3 72 Freescale Semiconductor FEC Electrical Characteristics Table 35 provides information on the MII and RMII transmit signal timing. Table 35. MII Transmit Signal Timing Num M5 M6 Characteristic MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid Min 5 -- 4 2 35% Max -- 25 -- -- 65% Unit ns ns ns ns MII_TX_CLK or RMII_REFCLK period MII_TX_CLK or RMII_REFCLK period M20_R RMII_TXD[1:0], RMII_TX_EN to RMII_REFCLK setup MII M21_R RMII_TXD[1:0], RMII_TX_EN data hold from RMII_REFCLK rising MII edge M7 MII_TX_CLK and RMII_REFCLK pulse width high M8 MII_TX_CLK and RMII_REFCLK pulse width low 35% 65% Figure 73 shows the MII transmit signal timing diagram. M7 MII_TX_CLK (input) RMII_REFCLK M5 M8 MII_TXD[3:0] (outputs) MII_TX_EN MII_TX_ER M6 Figure 73. MII Transmit Signal Timing Diagram 15.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL) Table 36 provides information on the MII async inputs signal timing. Table 36. MII Async Inputs Signal Timing Num M9 Characteristic MII_CRS, MII_COL minimum pulse width Min 1.5 Max -- Unit MII_TX_CLK period MPC885/MPC880 Hardware Specifications, Rev. 3 73 Freescale Semiconductor FEC Electrical Characteristics Figure 74 shows the MII asynchronous inputs signal timing diagram. MII_CRS, MII_COL M9 Figure 74. MII Async Inputs Timing Diagram 15.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC) Table 37 provides information on the MII serial management channel signal timing. The FEC functions correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation. Table 37. MII Serial Management Channel Timing Num M10 M11 M12 M13 M14 M15 Characteristic MII_MDC falling edge to MII_MDIO output invalid (minimum propagation delay) MII_MDC falling edge to MII_MDIO output valid (max prop delay) MII_MDIO (input) to MII_MDC rising edge setup MII_MDIO (input) to MII_MDC rising edge hold MII_MDC pulse width high MII_MDC pulse width low Min 0 -- 10 0 40% 40% Max -- 25 -- -- 60% 60% Unit ns ns ns ns MII_MDC period MII_MDC period Figure 75 shows the MII serial management channel timing diagram. M14 MM15 MII_MDC (output) M10 MII_MDIO (output) M11 MII_MDIO (input) M12 M13 Figure 75. MII Serial Management Channel Timing Diagram MPC885/MPC880 Hardware Specifications, Rev. 3 74 Freescale Semiconductor Mechanical Data and Ordering Information 16 Mechanical Data and Ordering Information Table 38 identifies the available packages and operating frequencies for the MPC885/880 derivative devices. Table 38. Available MPC885/880 Packages/Frequencies Package Type Plastic ball grid array ZP suffix -- Leaded VR suffix -- Lead-Free are available as needed Temperature (Tj) Frequency (MHz) 0C to 95C 66 Order Number KMPC885ZP66 KMPC880ZP66 MPC885ZP66 MPC880ZP66 KMPC885ZP80 KMPC880ZP80 MPC885ZP80 MPC880ZP80 KMPC885ZP133 KMPC880ZP133 MPC885ZP133 MPC880ZP133 KMPC885CZP66 KMPC880CZP66 MPC885CZP66 MPC880CZP66 KMPC885CZP133 KMPC880CZP133 MPC885CZP133 MPC880CZP133 80 133 Plastic ball grid array CZP suffix -- Leaded CVR suffix -- Lead-Free are available as needed -40C to 100C 66 133 MPC885/MPC880 Hardware Specifications, Rev. 3 75 Freescale Semiconductor Mechanical Data and Ordering Information 16.1 Pin Assignments Figure 76 shows the top-view pinout of the PBGA package. For additional information, see the MPC885 PowerQUICC Family User's Manual. NOTE: This is the top view of the device. W TRST PA10 PB23 PA8 PC8 PA5 PB17 PA13 PC4 PA11 PE17 PE30 PE15 PD6 PD4 PD7 PA3 V PB28 TMS PB25 PC11 PB22 PA7 PB19 PC7 PB16 PC13 PE21 PE24 PE14 PD5 PE28 PE27 PB31 PE23 PE22 U PB27 PB14 TCK PB24 PC10 PB21 PA6 MII1_COL PC6 PB15 PE31 PD15 PD14 PD13 PD12 PA4 PA0 PD9 PA1 T PB29 PC12 TDO TDI PA9 PC9 PB20 PB18 MII1_CRS PC5 PD3 PE29 PE16 PE19 MII1_TXEN PA2 PE25 PD10 PE26 R PC15 PC14 PB26 GND VDDL VDDL VDDL VDDL VDDH PE20 PD8 PD11 PE18 P MII_MDIO PB30 PA14 PA12 VDDH GND VDDH VDDH GND IRQ7 IRQ1 D0 D8 N A2 A1 N/C PA15 GND VDDL IRQ0 D12 D13 D4 M A3 A5 A4 A0 VDDL VDDH D17 D23 D27 D1 L A7 A9 A8 A6 VDDH GND GND VDDL D9 D10 D11 D2 K A10 A11 A12 A13 VDDL GND VDDH D5 D14 D3 D15 J A14 A16 A15 A17 VDDL D22 D19 D16 D18 H A27 A19 A20 A24 VDDH GND D28 D6 D20 D21 G A21 A29 A23 TSIZ0 VDDL VDDH GND GND VDDH CLKOUT D26 D24 D25 F A25 A30 A22 BSA3 VDDH IPA2 D31 D7 D29 A18 A28 TSIZ1 WE1 VDDL VDDL VDDL VDDL VSSSYN IPA3 IPA6 D30 E D A26 A31 BSA0 GPL_AB2 CS6 CS3 WR BI BR IRQ6 IPB1 ALEB AS MODCK1 EXTAL RSTCONF IPA7 IPA4 IPA5 C BSA2 BSA1 WE2 CS4 CE2_A CS1 GPL_A5 TA BG BURST IPB3 IPB2 IRQ4 OP1 BADDR28 TEXP WAIT_B VSSSYN1 IPA1 B WE3 WE0 GPL_A0 CS7 CE1_A CS0 GPL_A4 TEA BB IRQ2 IPB4 IPB7 ALEA OP0 BADDR29 HRESET PORESET VDDLSYN IPA0 A OE GPL_AB3 CS5 CS2 GPL_B4 BDIP TS IRQ3 IPB5 IPB0 IPB6 BADDR30 MODCK2 EXTCLK XTAL SRESET WAIT_A 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 76. Pinout of the PBGA Package MPC885/MPC880 Hardware Specifications, Rev. 3 76 Freescale Semiconductor Mechanical Data and Ordering Information Table 39 contains a list of the MPC885 input and output signals and shows multiplexing and pin assignments. Table 39. Pin Assignments Name A[0:31] Pin Number Type M16, N18, N19, M19, M17, M18, L16, L19, L17, L18, K19, K18, K17, Bidirectional K16, J19, J17, J18, J16, E19, H18, H17, G19, F17, G17, H16, F19, D19, Three-state H19, E18, G18, F18, D18 P2, M1, L1, K2, N1, K4, H3, F2, P1, L4, L3, L2, N3, N2, K3, K1, J2, M4, Bidirectional J1, J3, H2, H1, J4, M3, G2, G1, G3, M2, H4, F1, E1, F3 Three-state G16 E17 D13 C10 A13 A12 C12 B12 D12 B10 C7 Bidirectional Three-state Bidirectional Three-state Bidirectional Three-state Bidirectional Three-state Output Bidirectional Active pull-up Bidirectional Active pull-up Open-drain Bidirectional Active pull-up Bidirectional Three-state Bidirectional Three-state D[0:31] TSIZ0 REG TSIZ1 RD/WR BURST BDIP GPL_B5 TS TA TEA BI IRQ2 RSV IRQ4 KR RETRY SPKROUT CR IRQ3 BR BG BB FRZ IRQ6 IRQ0 IRQ1 IRQ7 A11 D11 C11 B11 D10 N4 P3 P4 Input Bidirectional Bidirectional Bidirectional Active pull-up Bidirectional Input Input Input MPC885/MPC880 Hardware Specifications, Rev. 3 77 Freescale Semiconductor Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name CS[0:5] CS6 CE1_B CS7 CE2_B WE0 BS_B0 IORD WE1 BS_B1 IOWR WE2 BS_B2 PCOE WE3 BS_B3 PCWE BS_A[0:3] GPL_A0 GPL_B0 OE GPL_A1 GPL_B1 GPL_A[2:3] GPL_B[2:3] CS[2:3] UPWAITA GPL_A4 UPWAITB GPL_B4 GPL_A5 PORESET RSTCONF HRESET SRESET XTAL EXTAL CLKOUT EXTCLK Pin Number B14, C14, A15, D14, C16, A16 D15 B16 B18 Output Output Output Output Type E16 Output C17 Output B19 Output D17, C18, C19, F16 B17 A18 Output Output Output D16, A17 Output B13 A14 C13 B3 D4 B4 A3 A4 D5 G4 A5 Bidirectional Bidirectional Output Input Input Open-drain Open-drain Analog output Analog input (3.3 V only) Output Input (3.3 V only) MPC885/MPC880 Hardware Specifications, Rev. 3 78 Freescale Semiconductor Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name TEXP ALE_A CE1_A CE2_A WAIT_A SOC_Split1 WAIT_B IP_A0 UTPB_Split01 IP_A1 UTPB_Split11 IP_A2 IOIS16_A UTPB_Split21 IP_A3 UTPB_Split31 IP_A4 UTPB_Split41 IP_A5 UTPB_Split51 IP_A6 UTPB_Split61 IP_A7 UTPB_Split71 ALE_B DSCK/AT1 IP_B[0:1] IWP[0:1] VFLS[0:1] IP_B2 IOIS16_B AT2 IP_B3 IWP2 VF2 IP_B4 LWP0 VF0 IP_B5 LWP1 VF1 C4 B7 B15 C15 A2 C3 B1 C1 F4 Pin Number Output Output Output Output Input Input Input Input Input Type E3 D2 D1 E2 D3 D8 A9, D9 Input Input Input Input Input Bidirectional Three-state Bidirectional C8 Bidirectional Three-state Bidirectional C9 B9 Bidirectional A10 Bidirectional MPC885/MPC880 Hardware Specifications, Rev. 3 79 Freescale Semiconductor Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name IP_B6 DSDI AT0 IP_B7 PTR AT3 OP0 UtpClk_Split1 OP1 OP2 MODCK1 STS OP3 MODCK2 DSDO BADDR30 REG BADDR[28:29] AS PA15 USBRXD PA14 USBOE PA13 RXD2 PA12 TXD2 PA11 RXD4 MII1-TXD0 RMII1-TXD0 PA10 MII1-TXER TIN4 CLK7 PA9 L1TXDA RXD3 PA8 L1RXDA TXD3 A8 Pin Number Type Bidirectional Three-state Bidirectional Three-state Bidirectional Output Bidirectional B8 B6 C6 D6 A6 Bidirectional A7 C5, B5 D7 N16 P17 W11 P16 W9 Output Output Input Bidirectional Bidirectional (Optional: open-drain) Bidirectional Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) W17 Bidirectional (Optional: open-drain) T15 Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) W15 MPC885/MPC880 Hardware Specifications, Rev. 3 80 Freescale Semiconductor Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name PA7 CLK1 L1RCLKA BRGO1 TIN1 PA6 CLK2 TOUT1 PA5 CLK3 L1TCLKA BRGO2 TIN2 PA4 CTS4 MII1-TXD1 RMII1-TXD1 PA3 MII1-RXER RMII1-RXER BRGO3 V14 Pin Number Type Bidirectional U13 Bidirectional W13 Bidirectional U4 Bidirectional W2 Bidirectional PA2 T4 MII1-RXDV RMII1-CRS_DV TXD4 PA1 MII1-RXD0 RMII1-RXD0 BRGO4 PA0 MII1-RXD1 RMII1-RXD1 TOUT4 PB31 SPISEL MII1 - TXCLK RMII1-REFCLK PB30 SPICLK PB29 SPIMOSI PB28 SPIMISO BRGO4 U1 Bidirectional Bidirectional U3 Bidirectional V3 Bidirectional (Optional: open-drain) P18 T19 V19 Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) MPC885/MPC880 Hardware Specifications, Rev. 3 81 Freescale Semiconductor Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name PB27 I2CSDA BRGO1 PB26 I2CSCL BRGO2 PB25 RXADDR31 TXADDR3 SMTXD1 PB24 TXADDR31 RXADDR3 SMRXD1 PB23 TXADDR21 RXADDR2 SDACK1 SMSYN1 PB22 TXADDR41 RXADDR4 SDACK2 SMSYN2 PB21 SMTXD2 TXADDR1 1 BRG01 RXADDR1 PHSEL[1] PB20 SMRXD2 L1CLKOA TXADDR01 RXADDR0 PHSEL[0] PB19 MII1-RXD3 RTS4 PB18 RXADDR41 TXADDR4 RTS2 L1ST2 U19 Pin Number Type Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) R17 V17 U16 Bidirectional (Optional: open-drain) W16 Bidirectional (Optional: open-drain) V15 Bidirectional (Optional: open-drain) U14 Bidirectional (Optional: open-drain) T13 Bidirectional (Optional: open-drain) V13 Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) T12 MPC885/MPC880 Hardware Specifications, Rev. 3 82 Freescale Semiconductor Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name PB17 L1ST3 BRGO2 RXADDR11 TXADDR1 PHREQ[1] PB16 L1RQa L1ST4 RTS4 RXADDR01 TXADDR0 PHREQ[0] PB15 TXCLAV BRG03 RXCLAV PB14 RXADDR21 TXADDR2 PC15 DREQ0 RTS3 L1ST1 TXCLAV RXCLAV PC14 DREQ1 RTS2 L1ST2 PC13 MII1-TXD3 SDACK1 PC12 MII1-TXD2 TOUT1 PC11 USBRXP PC10 USBRXN TGATE1 PC9 CTS2 PC8 CD2 TGATE2 W12 Pin Number Type Bidirectional (Optional: open-drain) V11 Bidirectional (Optional: open-drain) U10 Bidirectional U18 Bidirectional R19 Bidirectional R18 Bidirectional V10 Bidirectional T18 Bidirectional V16 U15 Bidirectional Bidirectional T14 W14 Bidirectional Bidirectional MPC885/MPC880 Hardware Specifications, Rev. 3 83 Freescale Semiconductor Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name PC7 CTS4 L1TSYNCB USBTXP PC6 CD4 L1RSYNCB USBTXN PC5 CTS3 L1TSYNCA SDACK2 PC4 CD3 L1RSYNCA PD15 L1TSYNCA UTPB0 PD14 L1RSYNCA UTPB1 PD13 L1TSYNCB UTPB2 PD12 L1RSYNCB UTPB3 PD11 RXD3 RXENB PD10 TXD3 TXENB PD9 TXD4 UTPCLK PD8 RXD4 MII-MDC RMII-MDC PD7 RTS3 UTPB4 V12 Pin Number Type Bidirectional U11 Bidirectional T10 Bidirectional W10 Bidirectional U8 Bidirectional U7 Bidirectional U6 Bidirectional U5 Bidirectional R2 Bidirectional T2 Bidirectional U2 Bidirectional R3 Bidirectional W3 Bidirectional MPC885/MPC880 Hardware Specifications, Rev. 3 84 Freescale Semiconductor Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name PD6 RTS4 UTPB5 PD5 CLK8 L1TCLKB UTPB6 PD4 CLK4 UTPB7 PD3 CLK7 TIN4 SOC PE31 CLK8 L1TCLKB MII1-RXCLK PE30 L1RXDB MII1-RXD2 PE29 MII2-CRS PE28 TOUT3 MII2-COL PE27 RTS3 L1RQB MII2-RXER RMII2-RXER W5 Pin Number Type Bidirectional V6 Bidirectional W4 Bidirectional T9 Bidirectional U9 Bidirectional (Optional: open-drain) W7 Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) T8 V5 V4 PE26 T1 L1CLKOB MII2-RXDV RMII2-CRS_DV PE25 RXD4 MII2-RXD3 L1ST2 PE24 SMRXD1 BRGO1 MII2-RXD2 T3 Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) V8 Bidirectional (Optional: open-drain) MPC885/MPC880 Hardware Specifications, Rev. 3 85 Freescale Semiconductor Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name PE23 SMSYN2 TXD4 MII2-RXCLK L1ST1 PE22 TOUT2 MII2-RXD1 RMII2-RXD1 SDACK1 PE21 SMRXD2 TOUT1 MII2-RXD0 RMII2-RXD0 RTS3 PE20 L1RSYNCA SMTXD2 CTS3 MII2-TXER PE19 L1TXDB MII2-TXEN RMII2-TXEN PE18 L1TSYNCA SMTXD1 MII2-TXD3 PE17 TIN3 CLK5 BRGO3 SMSYN1 MII2-TXD2 PE16 L1RCLKB CLK6 TXD3 MII2-TXCLK RMII2-REFCLK PE15 TGATE1 MII2-TXD1 RMII2-TXD1 V2 Pin Number Type Bidirectional (Optional: open-drain) V1 Bidirectional (Optional: open-drain) V9 Bidirectional (Optional: open-drain) R4 Bidirectional (Optional: open-drain) T6 Bidirectional (Optional: open-drain) R1 Bidirectional (Optional: open-drain) W8 Bidirectional (Optional: open-drain) T7 Bidirectional (Optional: open-drain) W6 Bidirectional MPC885/MPC880 Hardware Specifications, Rev. 3 86 Freescale Semiconductor Mechanical Data and Ordering Information Table 39. Pin Assignments (continued) Name PE14 RXD3 MII2-TXD0 RMII2-TXD0 TMS TDI DSDI TCK DSCK TRST TDO DSDO MII1_CRS MII_MDIO MII1_TXEN RMII1_TXEN MII1_COL VSSSYN1 VSSSYN VDDLSYN GND V7 Pin Number Type Bidirectional V18 T16 U17 W18 T17 T11 P19 T5 U12 C2 E4 B2 Input Input Input Input Output Input Bidirectional Output Input PLL analog VDD and GND Power Power G6, G7, G8, G9, G10, G11, G12, G13, H7, H8, H9, H10, H11, H12, H13, Power H14, J7, J8, J9, J10, J11, J12, J13, K7, K8, K9, K10, K11, K12, K13, L7, L8, L9, L10, L11, L12, L13, M7, M8, M9, M10, M11, M12, M13, N7, N8, N9, N10, N11, N12, N13, N14, P7, P13, R16 E5, E6, E9, E11, E14, G15, H5, J5, J15, K15, L5, M15, N5, R6, R9, R10, Power R12, R15 E7, E8, E10, E12, E13, E15, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, G5, G14, H6, H15, J6, J14, K5, K6, K14, L6, L14, L15, M5, M6, M14, N6, N15, P5, P6, P8, P9, P10, P11, P12, P14, P15, R5, R7, R8, R11, R13, R14 N17 mode only. Power VDDL VDDH N/C 1 ESAR No-connect MPC885/MPC880 Hardware Specifications, Rev. 3 87 Freescale Semiconductor Mechanical Data and Ordering Information 16.2 Mechanical Dimensions of the PBGA Package Figure 77 shows the mechanical dimensions of the PBGA package. NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M--1994. 3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. Figure 77. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package MPC885/MPC880 Hardware Specifications, Rev. 3 88 Freescale Semiconductor Document Revision History 17 Document Revision History Table 40 lists significant changes between revisions of this hardware specification. Table 40. Document Revision History Revision Number 0 0.1 Date 02/2003 04/2003 Initial revision. Added pinout and pinout assignments table. Added the USB timing to Section 14. Added the Reduced MII to Section 15. Removed the Data Parity. Made some changes to the Features list. Made the changes to the RMII Timing, Made sure all the VDDL, VDDH, and GND show up on the pinout diagram. Changed the SPI Master Timing Specs. 162 and 164. Corrected the signals that had overlines on them. Changed the pin descriptions for PD8 and PD9. Changed some more typos, put in the phsel and phreq pins. Corrected the USB timing. Changed the pin descriptions per the June 22 spec. Added the RxClav and TxClav signals to PC15. Added the Reference to USB 2.0 to the Features list and removed 1.1 from USB on the block diagrams. Changed the USB description to full-/low-speed compatible. Added the DSP information in the Features list Fixed table formatting. Nontechnical edits. Released to the external web. Changed the maximum operating frequency to 133 MHz. Put in the orderable part numbers that are orderable. Put the timing in the 80 MHz column. Rounded the timings to hundredths in the 80 MHz column. Put the pin numbers in footnotes by the maximum currents in Table 6. Changed 22 and 41 in the Timing. Put in the Thermal numbers. * Added sentence to Spec B1A about EXTCLK and CLKOUT being in Alignment for Integer Values * Added a footnote to Spec 41 specifying that EDM = 1 * Added RMII1_EN under M1II_EN in Table 36 Pin Assignments * Added a tablefootnote to Table 6 DC Electrical Specifications about meeting the VIL Max of the I2C Standard * Put the new part numbers in the Ordering Information Section Changes 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 05/2003 05/2003 5/2003 5/2003 6/2003 7/2003 8/2003 8/2003 9/2003 2.0 12/2003 3.0 7/22/2004 MPC885/MPC880 Hardware Specifications, Rev. 3 89 Freescale Semiconductor Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC885/MPC880 Hardware Specifications, Rev. 3 90 Freescale Semiconductor Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC885/MPC880 Hardware Specifications, Rev. 3 Freescale Semiconductor 91 How to Reach Us: USA/Europe/Locations Not Listed: Freescale Semiconductor Literature Distribution Center P.O. Box 5405, Denver, Colorado 80217 1-480-768-2130 (800) 521-6274 Japan: Freescale Semiconductor Japan Ltd. Technical Information Center 3-20-1, Minami-Azabu, Minato-ku Tokyo 106-8573, Japan 81-3-3440-3569 Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T. Hong Kong 852-26668334 Home Page: www.freescale.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Learn More: For more information about Freescale Semiconductor products, please visit www.freescale.com FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The described product contains a PowerPC processor core. The PowerPC name is a trademark of IBM Corp. and used under license. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2004. MPC885EC Rev. 3 07/2004 |
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